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ADV473 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADV473
Beschreibung CMOS 135 MHz True-Color Graphics Triple 8-Bit Video RAM-DAC
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 12 Seiten
ADV473 Datasheet, Funktion
a
CMOS 135 MHz True-Color Graphics
Triple 8-Bit Video RAM-DAC
ADV473
FEATURES
ADV478/ADV471 (ADV®) Register Level Compatible
IBM PS/2,* VGA*/XGA* Compatible
135 MHz Pipelined Operation
Triple 8-Bit D/A Converters
Triple 256 ؋ 8 (256 ؋ 24) Color Palette RAM
Three 15 ؋ 8 Overlay Registers
On-Board Voltage Reference
RS-343A/RS-170 Compatible Analog Outputs
TTL Compatible Digital Inputs and Outputs
Sync on All Three Channels
Programmable Pedestal (0 or 7.5 IRE)
Standard MPU l/O Interface
+5 V CMOS Monolithic Construction
68-Pin PLCC Package
APPLICATIONS
High Resolution Color Graphics
True-Color Visualization
CAE/CAD/CAM
Image Processing
Desktop Publishing
MODES
24-Bit True Color
8-Bit Pseudo Color
15-Bit True Color
8-Bit True Color
SPEED GRADES
135 MHz, 110 MHz
80 MHz, 66 MHz
GENERAL DESCRIPTION
The ADV473 is a complete analog output, Video RAM-DAC
on a single CMOS monolithic chip. The part is specifically
designed for true-color computer graphics systems.
The ADV473 integrates a number of graphic functions onto one
device allowing 24-bit direct true-color operation at the maxi-
mum screen update rate of 135 MHz. It can also be used in
other modes, including 15-bit true color and 8-bit pseudo or in-
dexed color. The ADV473 is fully PS/2 and VGA register level
compatible. It is also capable of implementing IBM’s XGA
standard.
(Continued on page 4)
FUNCTIONAL BLOCK DIAGRAM
VREFIN
VREFOUT
SYNC
BLANK
S0
S1
OL0
OVERLAYS
OL3
R0
RED
R7
G0
GREEN
G7
B0
BLUE
B7
P
I
4X
E
L
P
8 O8
R
T
88
88
SWITCHING
MATRIX &
PIXEL
MASK
8
8
8
OVERLAY PALETTE
15 x 8 RAM
15 x 8 RAM
15 x 8 RAM
8 88
RED
256 x 8
RAM
COLOR
PALETTE
GREEN
256 x 8
RAM
BLUE
256 x 8
RAM
8
8
8
8
8
8
COLOR
PALETTE/
OVERLAY
PALETTE
SWITCHER
8
8
8
D
A
C
P
O
R
T
VOLTAGE
REFERENCE
GENERATOR
VOLTAGE
REFERENCE
CONTROL
CIRCUIT
8 RED
DAC
8 GREEN
DAC
8 BLUE
DAC
OPA
IOR
IOG
IOB
CLOCK
MODE CONTROL PIXEL MASK
REGISTERS
REGISTERS
8
RED
REG
8
GREEN
REG
8
BLUE
REG
MPU PORT
8
ADDRESS
REG
MPU & PIXEL
PORT
CONTROL LOGIC
ADV473
CR0
CR1
CR2
CR3
D0–D7
RD WR RS0 RS1 RS2
ADV is a registered trademark of Analog Devices Inc.
*Personal System/2 and VGA are trademarks of International Business Machines Corp.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADV473 Datasheet, Funktion
ADV473
TERMINOLOGY
BLANKING LEVEL
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the pic-
ture tube, resulting in the blackest possible picture.
COLOR VIDEO (RGB)
This usually refers to the technique of combining the three pri-
mary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
COMPOSITE SYNC SIGNAL (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
COMPOSITE VIDEO SIGNAL
The video signal with or without setup, plus the composite
SYNC signal.
GRAY SCALE
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different lev-
els while a 6-bit DAC contains 64.
RASTER SCAN
The most basic method of sweeping a CRT one line at a time to
generate and to display images.
REFERENCE BLACK LEVEL
The maximum negative polarity amplitude of the video signal.
REFERENCE WHITE LEVEL
The maximum positive polarity amplitude of the video signal.
SETUP
The difference between the reference black level and the blank-
ing level.
SYNC LEVEL
The peak level of the composite SYNC signal.
VIDEO SIGNAL
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
CIRCUIT DESCRIPTION
MPU Interface
The ADV473 supports a standard MPU bus interface, allowing
the MPU direct access to the color palette RAM and overlay
color registers.
Three address decode lines, RS0–RS2, specify whether the
MPU is accessing the address register, the color palette RAM,
the overlay registers, or read mask register. These controls also
determine whether this access is a read or write function. Table
I illustrates this decoding. The 8-bit address register is used to
address the contents of the color palette RAM and overlay
registers.
Table I. Control Input Truth Table
RS2 RS1 RS0 Addressed by MPU
0 0 0 Address Register (RAM Write Mode)
0 1 1 Address Register (RAM Read Mode)
0 0 1 Color Palette RAM
0 1 0 Pixel Read Mask Register
1 0 0 Address Register (Overlay Write Mode)
1 1 1 Address Register (Overlay Read Mode)
1 0 1 Overlay Registers
1 1 0 Command Register
Color Palette Writes
The MPU writes to the address register (selecting RAM write
mode, RS2 = 0, RS1 = 0 and RS0 = 0) with the address of the
color palette RAM location to be modified. The MPU performs
three successive write cycles (8 or 6 bits each of red, green, and
blue), using RS0–RS2 to select the color palette RAM (RS2 =
0, RS1 = 0, RS0 = 1). After the BLUE write cycle, the three
bytes of color information are concatenated into a 24-bit word
or an 18-bit word and written to the location specified by the
address register. The address register then increments to the
next location which the MPU may modify by simply writing an-
other sequence of red, green, and blue data. A complete set of
colors can be loaded into the palette by initially writing the start
address and then performing a sequence of RED, GREEN and
BLUE writes. The address automatically increments to the next
highest location after a BLUE write.
Color Palette Reads
The MPU writes to the address register (selecting RAM read
mode, RS2 = 0, RS1 = 1 and RS0 = 1) with the address of the
color palette RAM location to be read back. The contents of the
palette RAM are copied to the RED, GREEN and BLUE regis-
ters and the address register increments to point to the next pal-
ette RAM location. The MPU then performs three successive
read cycles (8 or 6 bits each of red, green, and blue), using
RS0–RS2 to select the color palette RAM (RS2 = 0, RS1 = 0,
RS0 = 1). After the BLUE read cycle, the 24/18 bit contents of
the palette RAM at the location specified by the address register
is loaded into the RED, GREEN and BLUE registers. The ad-
dress register then increments to the next location which the
MPU can read back by simply reading another sequence of red,
green, and blue data. A complete set of colors can be read back
from the palette by initially writing the start address and then
performing a sequence of RED, GREEN and BLUE reads. The
address automatically increments to the next highest location
after a BLUE read.
–6– REV. A

6 Page









ADV473 pdf, datenblatt
ADV473
Analog Signal Interconnect
The ADV473 should be located as close as possible to the out-
put connectors to minimize noise pickup and reflections due to
impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
For maximum performance, the analog outputs should each
have a 75 load resistor connected to GND. The connection
between the current output and GND should be as close as pos-
sible to the ADV473 to minimize reflections.
For more information on circuit board design and layout, see
application note entitled “Design and Layout of a Video Graph-
ics System for Reduced EMI” available from Analog Devices,
Publication No. E1309-15-10/89.
0.1µF
0.1µF
POWER SUPPLY DECOUPLING
(0.1µF CAPACITOR FOR
EACH VREF GROUP)
+5V (VAA)
0.1µF
ANALOG POWER PLANE +5V (VAA)
+5V (VCC)
VAA
COMP
COMP
10µF
L1
(FERRITE
BEAD)
0.1µF
VREFOUT
VREFIN
0.1µF
RSET
140
ADV473
RSET
IOR
IOG
IOB
GND
75
CO-AXIAL CABLE
(75)
75
75
75
75
75BNC
CONNECTORS
MONITOR
(CRT)
COMPONENT
C1 – C5
C6
L1
R1, R2, R3
RSET
DESCRIPTION
0.1µF CERAMIC CAPACITOR
10µF TANTALUM CAPACITOR
FERRITE BEAD
751% METAL FILM RESISTOR
1% METAL FILM RESISTOR
VENDOR PART NUMBER
ERIE RPE112Z5U104M50V
MALLORY CSR13G106KM
FAIR-RITE 2743001111
Package Thermal Considerations
In certain circumstances, the 135 MHz version of the ADV473
may require forced air cooling or the addition of a heatsink. The
68-pin PLCC has a heat resistance characteristic as shown in
Table VIII.
It should be noted that information on Package Thermal Characteris-
tics published herein may not be the most up to date at the time of
reading this. Advances in packaging technology will inevitably lead
to improvements in thermal data. Please contact your local sales office
for the most up-to-date information.
Table VIII. Thermal Resistance vs. Airflow
Air Velocity
(Linear Feet/Min) 0 (Still Air) 50
100 200
θJA (°C/W)
32
26 19 16
9
10
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Plastic Leaded Chip Carrier
(P-68A)
0.995 (25.27)
0.885 (22.48) SQ
PIN 1
IDENTIFIER
61
60
0.175 (4.45)
0.169 (4.29)
0.050
(1.27)
TYP
0.925 (23.50)
0.895 (22.73)
TOP VIEW
0.019 (0.48)
0.017 (0.43)
26
27
0.954 (24.23)
0.950 (24.13) SQ
44
43
0.029 (0.74)
0.027 (0.69)
0.104 (2.64) TYP
Figure 8. Typical Connection Diagram (Internal Voltage
Reference)
–12–
REV. A

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