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ADUC834 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADUC834
Beschreibung MicroConverter/ Dual 16-/24- Bit ADCs with Embedded 62KB FLASH MCU
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADUC834 Datasheet, Funktion
www.DataSheet4U.com
a MicroConverter®, Dual 16-Bit/24-Bit -
ADCs with Embedded 62 kB Flash MCU
ADuC834
FEATURES
High Resolution -ADCs
2 Independent ADCs (16-Bit and 24-Bit Resolution)
24-Bit No Missing Codes, Primary ADC
21-Bit rms (18.5-Bit p-p) Effective Resolution @ 20 Hz
Offset Drift 10 nV/؇C, Gain Drift 0.5 ppm/؇C
Memory
62 Kbytes On-Chip Flash/EE Program Memory
4 Kbytes On-Chip Flash/EE Data Memory
Flash/EE, 100 Year Retention, 100 Kcycles Endurance
3 Levels of Flash/EE Program Memory Security
In-Circuit Serial Download (No External Hardware)
High Speed User Download (5 Seconds)
2304 Bytes On-Chip Data RAM
8051-Based Core
8051 Compatible Instruction Set
32 kHz External Crystal
On-Chip Programmable PLL (12.58 MHz Max)
3 ؋ 16-Bit Timer/Counter
26 Programmable I/O Lines
11 Interrupt Sources, Two Priority Levels
Dual Data Pointer, Extended 11-Bit Stack Pointer
On-Chip Peripherals
Internal Power on Reset Circuit
12-Bit Voltage Output DAC
Dual 16-Bit -DACs/PWMs
On-Chip Temperature Sensor
Dual Excitation Current Sources
Time Interval Counter (Wake-Up/RTC Timer)
UART, SPI®, and I2C® Serial I/O
High Speed Baud Rate Generator (Including 115,200)
Watchdog Timer (WDT)
Power Supply Monitor (PSM)
Power
Normal: 2.3 mA Max @ 3.6 V (Core CLK = 1.57 MHz)
Power-Down: 20 A Max with Wake-Up Timer Running
Specified for 3 V and 5 V Operation
Package and Temperature Range
52-Lead MQFP (14 mm ؋ 14 mm), –40؇C to +125؇C
56-Lead LFCSP (8 mm ؋ 8 mm), –40؇C to +85؇C
APPLICATIONS
Intelligent Sensors
Weigh Scales
Portable Instrumentation, Battery-Powered Systems
4–20 mA Transmitters
Data Logging
Precision System Monitoring
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
FUNCTIONAL BLOCK DIAGRAM
AIN1
AIN2
AIN3
AIN4
AIN5
REFIN–
REFIN+
RESET
DVDD
DGND
AVDD
ADuC834
MUX
BUF
PGA
PRIMARY
24-BIT -ADC
AVDD
CURRENT
SOURCE
12-BIT
DAC
BUF
IEXC1
IEXC2
DAC
MUX
AGND
TEMP
SENSOR
AUXILIARY
16-BIT -ADC
DUAL
16-BIT
-DAC
DUAL
16-BIT
PWM
MUX
EXTERNAL
VREF
DETECT
INTERNAL
BAND GAP
VREF
POR
8051-BASED MCU WITH ADDITIONAL
PERIPHERALS
62 KBYTES FLASH/EE PROGRAM MEMORY
4 KBYTES FLASH/EE DATA MEMORY
2304 BYTES USER RAM
PLL AND PROG
CLOCK DIV
3 ؋ 16 BIT TIMERS POWER SUPPLY MON
BAUD R ATE TIMER WATCHDOG TIMER
OSC
WAKE- UP/
RTC TIMER
4 ؋ PARALLEL
PORTS
UART, SPI, AND I2C
SERIAL I/O
PWM0
PWM1
XTAL1 XTAL2
GENERAL DESCRIPTION
The ADuC834 is a complete smart transducer front end,
integrating two high resolution -ADCs, an 8-bit MCU, and
program/data Flash/EE memory on a single chip.
The two independent ADCs (primary and auxiliary) include a
temperature sensor and a PGA (allowing direct measurement of
low level signals). The ADCs with on-chip digital filtering and
programmable output data rates are intended for the measurement
of wide dynamic range, low frequency signals, such as those in
weigh scale, strain-gage, pressure transducer, or temperature
measurement applications.
The device operates from a 32 kHz crystal with an on-chip PLL
generating a high frequency clock of 12.58 MHz. This clock is
routed through a programmable clock divider from which the MCU
core clock operating frequency is generated. The microcontroller
core is an 8052 and therefore 8051 instruction set compatible
with 12 core clock periods per machine cycle.
62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of
nonvolatile Flash/EE data memory, and 2304 bytes of data RAM
are provided on-chip. The program memory can be configured
as data memory to give up to 60 Kbytes of NV data memory in
data logging applications.
On-chip factory firmware supports in-circuit serial download and
debug modes (via UART), as well as single-pin emulation mode
via the EA pin. The ADuC834 is supported by a QuickStart™
development system featuring low cost software and hardware
development tools.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.






ADUC834 Datasheet, Funktion
ADuC834
SPECIFICATIONS (continued)
Parameter
ADuC834
LOGIC OUTPUTS (Not Including XTAL2)2
VOH, Output High Voltage
2.4
2.4
VOL, Output Low Voltage14
0.4
Floating State Leakage Current2
Floating State Output Capacitance
POWER SUPPLY MONITOR (PSM)
AVDD Trip Point Selection Range
AVDD Power Supply Trip Point Accuracy
DVDD Trip Point Selection Range
DVDD Power Supply Trip Point Accuracy
WATCHDOG TIMER (WDT)
Timeout Period
MCU CORE CLOCK RATE
MCU Clock Rate2
0.4
0.4
± 10
5
2.63
4.63
± 3.0
± 4.0
2.63
4.63
± 3.0
± 4.0
0
2000
98.3
12.58
START-UP TIME
At Power-On
After External RESET in Normal Mode
After WDT Reset in Normal Mode
From Idle Mode
From Power-Down Mode
Oscillator Running
Wake-Up with INT0 Interrupt
Wake-Up with SPI Interrupt
Wake-Up with TIC Interrupt
Wake-Up with External RESET
Oscillator Powered Down
Wake-Up with INT0 Interrupt
Wake-Up with SPI Interrupt
Wake-Up with External RESET
300
3
3
10
20
20
20
3
20
20
5
FLASH/EE MEMORY RELIABILITY CHARACTERISTICS15
Endurance16
100,000
Data Retention17
100
Test Conditions/Comments
Unit
VDD = 5 V, ISOURCE = 80 A
VDD = 3 V, ISOURCE = 20 A
ISINK = 8 mA, SCLOCK,
MOSI/SDATA
ISINK = 10 mA, P1.0 and P1.1
ISINK = 1.6 mA, All Other Outputs
V min
V min
V max
V max
V max
A max
pF typ
Four Trip Points Selectable in This Range
Programmed via TPA1–0 in PSMCON
TMAX = 85°C
TMAX = 125°C
Four Trip Points Selectable in This Range
Programmed via TPD1–0 in PSMCON
TMAX = 85ЊC
TMAX = 125ЊC
V min
V max
% max
% max
V min
V max
% max
% max
Nine Timeout Periods in This Range
Programmed via PRE3–0 in WDCON
Clock Rate Generated via On-Chip PLL
Programmable via CD2–0 Bits in
PLLCON SFR
ms min
ms max
kHz min
MHz max
Controlled via WDCON SFR
OSC_PD Bit = 0 in PLLCON SFR
OSC_PD Bit = 1 in PLLCON SFR
ms typ
ms typ
ms typ
s typ
s typ
s typ
s typ
ms typ
s typ
s typ
ms typ
Cycles min
Years min
–6– REV. A

6 Page









ADUC834 pdf, datenblatt
ADuC834
Pin No. Pin No.
52-Lead 56-Lead
MQFP CSP Mnemonic
28–31
36–39
30–33
39–42
P2.0–P2.7
(A8–A15)
(A16–A23)
32 34 XTAL1
33 35 XTAL2
40 43 EA
41 44 PSEN
42 45 ALE
43–46
49–52
46–49
52–55
P0.0–P0.7
(AD0–AD3)
(AD4–AD7)
*I = Input, O = Output, S = Supply.
PIN FUNCTION DESCRIPTIONS (continued)
Type* Description
I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s
written to them are pulled high by the internal pull-up resistors, and in that state can
be used as inputs. As inputs, Port 2 pins being pulled externally low will source current
because of the internal pull-up resistors.
Port 2 emits the high order address bytes during fetches from external program memory
and middle and high order address bytes during accesses to the 24-bit external data
memory space.
I Input to the Crystal Oscillator Inverter
O Output from the Crystal Oscillator Inverter. (See “Hardware Design Considerations”
for description.)
I/O External Access Enable, Logic Input. When held high, this input enables the device
to fetch code from internal program memory locations 0000h to F7FFh. When held
low, this input enables the device to fetch all instructions from external program
memory. To determine the mode of code execution, i.e., internal or external, the
EA pin is sampled at the end of an external RESET assertion or as part of a device
power cycle. EA may also be used as an external emulation I/O pin, and therefore
the voltage level at this pin must not be changed during normal mode operation
as it may cause an emulation interrupt that will halt code execution.
O Program Store Enable, Logic Output. This output is a control signal that enables
the external program memory to the bus during external fetch operations. It is
active every six oscillator periods except during external data memory accesses.
This pin remains high during internal program execution.
PSEN can also be used to enable serial download mode when pulled low through a
resistor at the end of an external RESET assertion or as part of a device power cycle.
O Address Latch Enable, Logic Output. This output is used to latch the low byte (and
page byte for 24-bit data address space accesses) of the address to external memory
during external code or data memory access cycles. It is activated every six oscillator
periods except during an external data memory access. It can be disabled by setting
the PCON.4 bit in the PCON SFR.
I/O P0.0–P0.7, these pins are part of Port0, which is an 8-bit, open-drain, bidirectional
I/O port. Port 0 pins that have 1s written to them float and in that state can be used
as high impedance inputs. An external pull-up resistor will be required on P0 outputs
to force a valid logic high level externally. Port 0 is also the multiplexed low-order
address and databus during accesses to external program or data memory. In this
application, it uses strong internal pull-ups when emitting 1s.
–12–
REV. A

12 Page





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