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PDF ADUC812 Data sheet ( Hoja de datos )
| Número de pieza | ADUC812 | |
| Descripción | MicroConverter/ Multichannel 12-Bit ADC with Embedded FLASH MCU | |
| Fabricantes | Analog Devices | |
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a
MicroConverter™, Multichannel
12-Bit ADC with Embedded FLASH MCU
ADuC812
FEATURES
APPLICATIONS
ANALOG I/O
Intelligent Sensors (IEEE 1451.2-Compatible)
8-Channel, High Accuracy 12-Bit ADC
Battery Powered Systems (Portable PCs, Instruments,
On-Chip, 40 ppm/؇C Voltage Reference
Monitors)
High Speed 200 kSPS
Transient Capture Systems
DMA Controller for High Speed ADC-to-RAM Capture
DAS and Communications Systems
Two 12-Bit Voltage Output DACs
On-Chip Temperature Sensor Function
MEMORY
8K Bytes On-Chip Flash/EE Program Memory
640 Bytes On-Chip Flash/EE Data Memory
On-Chip Charge Pump (No Ext. VPP Requirements)
256 Bytes On-Chip Data RAM
16M Bytes External Data Address Space
64K Bytes External Program Address Space
8051-COMPATIBLE CORE
12 MHz Nominal Operation (16 MHz Max)
Three 16-Bit Timer/Counters
32 Programmable I/O lines
High Current Drive Capability—Port 3
Nine Interrupt Sources, Two Priority Levels
POWER
Specified for 3 V and 5 V Operation
Normal, Idle and Power-Down Modes
ON-CHIP PERIPHERALS
UART Serial I/O
2-Wire (I2C®-Compatible) and SPI® Serial I/O
GENERAL DESCRIPTION
The ADuC812 is a fully integrated 12-bit data acquisition
system incorporating a high performance self-calibrating
multichannel ADC, two 12-bit DACs and programmable 8-bit
(8051-compatible) MCU on a single chip.
The programmable 8051-compatible core is supported by
8K bytes Flash/EE program memory, 640 bytes Flash/EE data
memory and 256 bytes data SRAM on-chip.
Additional MCU support functions include Watchdog Timer,
Power Supply Monitor and ADC DMA functions. 32 Program-
mable I/O lines, I2C-compatible, SPI and Standard UART
Serial Port I/O are provided for multiprocessor interfaces and
I/O expansion.
Normal, idle and power-down operating modes for both the
MCU core and analog converters allow for flexible power man-
agement schemes suited to low power applications. The part is
specified for 3 V and 5 V operation over the industrial tempera-
ture range and is available in a 52-lead, plastic quad flatpack
package.
Watchdog Timer
Power Supply Monitor
FUNCTIONAL BLOCK DIAGRAM
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
AIN0 (P1.0)
AIN7 (P1.7)
VREF
CREF
AIN
MUX
T/H
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
ADC
CONTROL
AND
CALIBRATION
LOGIC
2.5V
REF
TEMP
SENSOR
BUF
8051-COMPATIBLE
MICROCONTROLLER
8K BYTES FLASH/EE
PROGRAM MEMORY
640 BYTES FLASH/EE
DATA MEMORY
256 ؋ 8 USER
RAM
DAC
CONTROL
12-BIT
DAC0
12-BIT
DAC1
BUF ADuC812
BUF
MICROCONTROLLER
POWER SUPPLY
MONITOR
WATCHDOG
TIMER
ON-CHIP SERIAL
DOWN LOADER
OSC
UART
3 ؋ 16-BIT
TIMER/COUNTERS
2-WIRE
SERIAL I/O
SPI
MUX
DAC0
DAC1
T0 (P3.4)
T1 (P3.5)
T2 (P1.0)
T2EX (P1.1)
INT0 (P3.2)
INT1 (P3.3)
ALE
PSEN
EA
RESET
AVDD AGND DVDD DGND
I2C is a registered trademark of Philips Corporation.
MicroConverter is a trademark of Analog Devices, Inc.
SPI is a registered trademark of Motorola Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
XTAL XTAL TxD RxD SCLOCK MOSI/ MISO
1 2 (P3.0) (P3.1)
SDATA (P3.3)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DVDD to DGND, AVDD to AGND . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to DGND . . . . . –0.3 V, DVDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V, DVDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V
Analog Inputs to AGND . . . . . . . . . . . . –0.3 V, AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ADuC812
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
P1.0/ADC0/T2 1
P1.1/ADC1/T2EX 2
P1.2/ADC2 3
P1.3/ADC3 4
AVDD 5
AGND 6
CREF 7
VREF 8
DAC0 9
DAC1 10
P1.4/ADC4 11
P1.5/ADC5/SS 12
P1.6/ADC6 13
PIN 1
IDENTIFIER
ADuC812
TOP VIEW
(Not to Scale)
39 P2.7/A15/A23
38 P2.6/A14/A22
37 P2.5/A13/A21
36 P2.4/A12/A20
35 DGND
34 DVDD
33 XTAL2 (OUTPUT)
32 XTAL1 (INPUT)
31 P2.3/A11/A19
30 P2.2/A10/A18
29 P2.1/A9/A17
28 P2.0/A8/A16
27 SDATA/MOSI
14 15 16 17 18 19 20 21 22 23 24 25 26
Model
ADuC812BS
ORDERING GUIDE
Temperature
Range
–40°C to +85°C
Package
Description
52-Lead Plastic Quad Flatpack
QuickStart™ Development System
Eval-ADuC812QS
Package
Option
S-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADuC812 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
5 Page 
ADuC812
many applications this autocalibration download function suf-
fices. Alternatively, a device calibration can be easily initiated by
user software to compensate for significant changes in operating
conditions (CLK frequency, analog input range, reference volt-
age and supply voltages).
This in-circuit software calibration feature allows the user to
remove various system and reference related errors (whether it
be internal or external reference) and to make use of the full
dynamic range of the ADC by adjusting the analog input range
of the part for a specific system. Contact Analog Devices, Inc.
for further details on the implementation of the software calibra-
tion routine in your applications.
ADC MODES OF OPERATION
Typical Operation
Once configured via the ADCCON 1-3 SFRs (shown previ-
ously) the ADC will convert the analog input and provide an
ADC 12-bit result word in the ADCDATAH/L SFRs. The top
four bits of the ADCDATAH SFR will be written with the
channel selection bits to identify the channel result. The format
of the ADC 12-bit result word is shown in Figure 5.
ADCDATAH SFR
CH–ID
TOP 4 BITS
HIGH 4 BITS OF
ADC RESULT WORD
ADCDATAL SFR
LOW 8 BITS OF THE
ADC RESULT WORD
Figure 5. ADC Result Format
ADC DMA Mode
The on-chip ADC has been designed to run at a maximum speed
of one sample every 5 µs (i.e., 200 kHz sampling rate). Therefore,
in an interrupt driven routine the user software is required to ser-
vice the interrupt, read the ADC result and store the result for
further post processing, all within 5 µs otherwise the next ADC
sample could be lost. In applications where the ADuC812 can-
not sustain the interrupt rate, an ADC DMA Mode is provided.
The ADC DMA Mode is enabled via the DMA enable bit
(ADCCON2.6), which allows the ADC to sample continuously
as per configuration in ADCCON SFRs. Each sample result is
written into an external Static RAM (mapped in the data memory
space) without any interaction from the ADuC812 core. This
mode ensures the ADuC812 can capture a contiguous sample
stream even at full speed ADC update rates.
Before enabling ADC DMA mode the user must first configure
the external SRAM to which the ADC samples will be written.
This consists of writing the required ADC DMA channels into
the channel ID bits (the top four bits) in the external SRAM. A
typical preconfiguration of external memory is shown in Figure 6.
Once the external data memory has been preconfigured, the
DMA address pointer (DMAP, DMAH and DMAL) SFRs are
written. These SFRs should be written with the DMA start
address in external memory. In Figure 6, for example, the DMA
start address is 000000H. The 3-byte start address should be
written in the following order: DMAL, DMAH and DMAP.
The end of a DMA table is signified by writing “1111” into the
channel selection bits field.
00000AH 1 1 1 1
00 11
00 11
STOP COMMAND
REPEAT LAST CHANNEL
FOR A VALID STOP
CONDITION
CONVERT ADC CH#3
100 0
CONVERT TEMP SENSOR
010 1
CONVERT ADC CH#5
000000H 0 0 1 0
CONVERT ADC CH#2
Figure 6. Typical DMA External Memory Preconfiguration
The DMA Enable bit (ADCCON2.6, DMA) can now be set to
initiate the DMA conversion and transfer of the results sequen-
tially into external memory. Remember that the DMA mode
will only progress if the user has preconfigured the ADC
conversion time and trigger modes via the ADCCON1 and 2
SFRs. The end of DMA conversion is signified by the ADC
interrupt bit ADCCON2.7.
At the end of ADC DMA Mode, the external data memory
contains the new ADC conversion results as shown in Figure 7.
It should be noted that the channel selection bits are still present
in the result words to identify the individual conversion results.
00000AH 1 1 1 1
00 11
00 11
100 0
010 1
000000H 0 0 1 0
STOP COMMAND
NO CONVERSION
RESULT WRITTEN HERE
CONVERSION RESULT
FOR ADC CH#3
CONVERSION RESULT
FOR TEMP SENSOR
CONVERSION RESULT
FOR ADC CH#5
CONVERSION RESULT
FOR ADC CH#2
Figure 7. Typical External Memory Configuration Post
ADC DMA Operation
Micro Operation during ADC DMA Mode
During ADC DMA mode the MicroConverter core is free to
continue code execution, including general housekeeping and
communication tasks. However, it should be noted that MCU
core accesses to Ports 0 and 2 (which, of course, are being used
by the DMA controller) are gated “OFF” during ADC DMA
mode of operation. This means that even though the instruction
that accesses the external Ports 0 or 2 will appear to execute, no
data will be seen at these external port pins as a result.
The MicroConverter core is interrupted once the requested
block of DMA data has been captured and written to external
memory allowing the service routine for this interrupt to post-
process the data without any real time, timing constraints.
SFR Interface to the DAC Block
The ADuC812 incorporates two 12-bit DACs on-chip. DAC
operation is controlled via a single control special function
register and four data special function registers, namely:
DAC0L/DAC1L – Contains the lower 8-bit DAC byte.
DAC0H/DAC1H – Contains the high 4-bit DAC byte.
DACCON
– Contains general purpose control bits
required for DAC0 and DAC1 operation.
REV. 0
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADUC812.PDF ] | |
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