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PDF ADSST-21065LCS-240 Data sheet ( Hoja de datos )
| Número de pieza | ADSST-21065LCS-240 | |
| Descripción | High End/ Multichannel/ 32-Bit Floating-Point Audio Processor | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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a
High End, Multichannel,
32-Bit Floating-Point Audio Processor
SST-Melody®-SHARC®
FEATURES
Super Harvard Architecture Computer (SHARC)
4 Independent Buses for Dual Data, Instruction, and
I/O Fetch on a Single Cycle
32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-
Point Arithmetic
544 Kbits On-Chip SRAM Memory, Integrated I/O
Peripheral I2S Support for 8 Simultaneous Receive and
Transmit Channels
66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained
Performance
User-Configurable 544 Kbits On-Chip SRAM Memory
2 External Port, DMA Channels and 8 Serial Port,
DMA Channels
Decodes Industry Standard Formats Using a 32-Bit
Floating Point Implementation for Decoding
Dolby® Digital AC-3, Dolby Digital EX Processing
Dolby Pro Logic®, 96 kHz, Dolby Pro Logic II
Dolby Headphone, Dolby 3/0
DTS® 5.1, DTS-ES®-Discreet 6.1, DTS Matrix and Matrix 3.0,
DTS 96/24®, DTS NEO:6
THX® Ultra, Select, Ultra2, 5.1, 7.1, EX
SRS® Labs Circle Surround IITM, Virtual Loudspeaker
MPEG AAC, MPEG2 Decode, MPEG 2-Channel Decode
PCM, PCM 96 kHz
HDCD, MLP*
Delay 7.1, 96 kHz
Bass 7.1, 96 kHz, Bass/Treble 2 Channel
ADI Surround: Club, Music, and Stadium
AAC (LC), AAC (LC) 2 Channel, AAC MP
WaveSurround 5.1 Channel to Headphone, Stereo to
Headphone, Channel to Loudspeaker, Stereo to
Loudspeaker
Downsampling 96 kHz to 48 kHz (2-Channel)
3-Band Equalizer, 2-Channel
Encoders: AC-3 2-Channel Consumer Encoder
Single Chip DSP-Based Implementation of Digital Audio
Algorithms
I2S Compatible Ports
Interface to External SDRAM
Melody and SHARC are registered trademarks of Analog Devices, Inc.
DTS, DTS-ES, and DTS 96/24 are registered trademarks of Digital Theater
Systems, Inc.
Dolby and Pro Logic are registered trademarks of Dolby Laboratories
Licensing Corporation.
SRS is a registered trademark and Circle Surround II is a trademark of SRS Labs.
THX is a registered trademark of the THX, Ltd.
*MLP is implemented, not certified.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
SDRAM
128K ؋ 32,
BOOT ROM
1M ؋ 8
ADC
IRQ
GPIO
SST-Melody-SHARC
SERIAL PORT
DAC
ALGORITHMS
COMMAND
S/PDIF
TRANSMITTER
KERNEL
S/PDIF
RECEIVER
DMA CONNECTION
OR DUAL BUFFER
HOST MICRO
Easy Interfaces to Audio Codecs
96 kHz Processing
Supports Customer Specific Post Processing
Automatic Stream Detection and Code Loading
Easy to Use Software Architecture
Optimized Library of Routines
Host Communication Using 16-Bit Parallel Port or SPI Port
Highly Flexible Serial Ports
SRAM Interface for More Delay
Supports IEC60958 For Bit Streams
8-Channel Output Using TDM Codecs
APPLICATIONS
Home Theater AVR Systems
Automotive Audio Receivers
Video Game Consoles
DVD Players
Cable and Satellite Set-Top Boxes
Multimedia Audio/Video Gateways
GENERAL DESCRIPTION
The SST-Melody-SHARC family of powerful 32-bit Audio Proces-
sors from Analog Devices provides flexible solutions and delivers
a host of features across high end and high fidelity audio systems
to the AV receiver and DVD markets. It includes multichannel
audio decoders, encoders, and post processors for digital
audio designs using DSP chipsets in home theater systems and
automotive audio receivers.
(continued on page 11)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
196-BALL CSPBGA PIN CONFIGURATION
SST-Melody-SHARC
14
NC7
13 12 11 10
9
8
7
6
5
4
3
2
NC8 ADDR18 ADDR17 ADDR14 ADDR11 ADDR8 ADDR7 ADDR6 ADDR3 ADDR0 FLAG2 NC2
1
NC1 A
TCK
GND ADDR23 ADDR21 ADDR19 ADDR15 ADDR12 ADDR9 ADDR5 ADDR2 FLAG0 IRQ0
RFS0 DR0A B
TDO
BSEL RESET ADDR22 ADDR20 ADDR16 ADDR13 ADDR10 ADDR4 ADDR1 FLAG3 IRQ2 RCLK0 TCLK0 C
EMU
TRST
TMS
BMS
VDD
VDD
VDD
VDD
VDD FLAG1 IRQ1
DR0B
TFS0 RCLK1 D
FLAG4
ID1
TDI
ID0
VDD
GND
GND
GND
GND
VDD
RFS1 DT0A DT0B TFS1 E
FLAG7 FLAG5 FLAG6 VDD
GND
GND
GND
GND
GND
GND
VDD
DR1A DR1B TCLK1 F
DATA29 DATA30 DATA31 VDD
DATA26 DATA27 DATA28 VDD
DATA23 DATA25 DATA24 VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
VDD
DT1A
BR2
DT1B
PWM_ G
EVENT1
BR1
PWM_ H
EVENT0
VDD SDCLK1 XTAL CLKIN J
DATA22 DATA20 DATA21 DATA19 VDD
GND
GND
GND
GND
VDD
SDWE
HBR SDCLK0 DMAR1 K
DATA18 DATA17 DATA16 DATA13 DATA8 VDD
VDD
VDD
VDD
VDD DMAG2 SDA10 CAS DMAR2 L
DATA15 DATA14 DATA12 DATA9 DATA5 DATA2 FLAG10 ACK
CPA
RD
CS DMAG1 SDCKE RAS M
NC6 DATA11 DATA10 DATA7 DATA4 DATA1 FLAG11 MS1
GND REDY SBTS BMSTR HBG
DQM N
NC5 DATA6 DATA3 DATA0 FLAG8 FLAG9 MS3
MS2
MS0
SW
WR GND NC4 NC3 P
REV. 0
–5–
5 Page 
SST-Melody-SHARC
GENERAL DESCRIPTION (continued from page 1)
With 32-bit audio quality, the SST-Melody-SHARC audio
processor auto-detects and decodes audio formats in real-time,
enabling end users to enjoy a theater-quality audio experience in
their homes.
The solutions can be customized to meet the exact requirements
of the application. This audio DSP system allows designers to make
value additions to product features working off the high end base
functionality that they are provided with.
Evaluation boards, sample applications and all necessary software
support (drivers, and so on) are available. The SST-Melody-SHARC
enables OEMs to offer comprehensive and single chip solutions
for advanced features in products for end users. SST-Melody-
SHARC audio processors enable OEMs to produce high quality,
low cost designs featuring decoder algorithms and post processors
for DTS-ES Extended Surround (including both DTS-ES Dis-
creet 6.1 and DTS-ES Matrix 6.1), DTS Neo:6, Dolby Digital,
Dolby Digital EX, Dolby Pro Logic, Dolby Pro Logic II, Dolby
Headphone, DDCE, THX and THX Surround EX, HDCD,
MPEG1 Audio Layer 3 (also known as MP3), MPEG2 Audio,
AAC, MLP, WaveSurround, SRS 3D Sound and Stereo. The
audio processors also include audio encoders for DDCE, MPEG,
and MP3.
The cost of development is reduced with the scalable family of
code-compatible devices enabling common solutions across
product lines. Field upgradeable products with programmable
DSP and an optimized library of routines including Dolby and
DTS suites, multichannel AAC and all others, along with the
best development tools in the industry, reduce the time to market.
SST-Melody-SHARC is the comprehensive answer to the needs
of the high end, high quality digital audio market. It delivers a
realistic high fidelity audio experience along with a maximum num-
ber of features, across price points in the high end DVD markets.
HARDWARE ARCHITECTURE
Hardware architecture covers the interface between DSP and
host microcontroller, command processing, data transfer in
serial and parallel form, data buffer management, algorithm
combinations, MIPS, and memory requirements that are provided.
The multichannel algorithms are implemented and tested on a
demo board “PEGASUS II.” This stand-alone board accepts
compressed digital bit streams as serial input from LD/DVD/CD
players or any stream generator and decodes in real time to
generate a 2-channel or multichannel PCM stream. It has a
microcontroller to scan a small keypad to give commands and
select various options, and an LCD for status display.
The SST-Melody-SHARC family (SST-Melody-SHARC) hard-
ware architecture can be broken up into four blocks:
• The Core Processor
• Dual-Ported SAAM
• External Port
• Input/Output Processor
The hardware architecture of the Melody SHARC is complex.
It has four independent buses for dual data, one for instructions,
and one for I/O fetch. Since the four buses are independent,
multiple transactions take place in a single clock cycle. It has two
external ports, DMA channels, and eight serial ports. It is a
0.35 µm technology IC operating at 3.3 V.
The SST-Melody-SHARC processor can be interfaced to external
peripherals with relative ease. The communication between the
SST-Melody-SHARC processor and a host microcontroller utilizes
the SPI bus. The host microcontroller can be the master and the
SST-Melody-SHARC processor can act as a slave. The peripher-
als can be controlled by the host microcontroller using the SPI
bus. The communication is based on commands and parameters.
Status information regarding the SST-Melody-SHARC decoding is
periodically updated and made available to the host microcontroller.
The block diagram of the SST-Melody-SHARC illustrates the
following architectural features:
• Computation units (ALU, multiplier, and shifter) with a shared
data register file
• Data address generators (DAG1, DAG2)
• Program sequencer with instruction cache
• Timers with event capture modes
• On-chip, dual-ported SRAM
• External port for interfacing to off-chip memory and
peripherals
• Host port and SDRAM interface
• DMA controller
• Enhanced serial ports
• JTAG test access port
We will use the Functional Block Diagram as our reference. We
assume the SST-Melody-SHARC communicates with host micro
using either direct DMA access or a dual buffer hardware
mechanism. SST-Melody-SHARC has an on-chip memory
buffer that is used for storing commands/parameters sent by the
host to SST-Melody-SHARC and also status information from
SST-Melody-SHARC to be sent to host micro. SST-Melody-
SHARC has direct access to this memory buffer as it resides
on-chip. Host micro has access to this memory using either
direct DMA access or a dual buffer hardware mechanism.
There is a definite protocol for passing commands and obtaining
status information. Once SST-Melody-SHARC receives a com-
mand from host micro, it will process the same and inform host
micro of the status. These commands initiate actions like encoding
and decoding. Encoding and decoding will result in data process-
ing and the processed data may be delivered over the serial port.
For example, while encoding, the PCM data is accepted through
the serial port from peripherals like an ADC or S/PDIF receiver.
The PCM data is then encoded and stored in an on-chip com-
pressed data buffer. These compressed frames are then
accessible to host micro using a high speed DMA or USB port.
SST-Melody-SHARC, will prepare the compressed frames in the
form of IEC 958 format so that it can be sent out using the serial
port or S/PDIF transmitter. Compressed frames can be down-
loaded by host micro to SST-Melody-SHARC and can be
decoded and the resulting PCM data can be sent on serial port
transmitter. While commands and data are transferred between
host micro and SST-Melody-SHARC over a dual buffer/DMA we
need the help of interrupts and a few general-purpose input/
output lines to provide reliable communication.
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ADSST-21065LCS-240.PDF ] | |
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