ADSP-BF561SKBCZ500 Datasheet PDF - Analog Devices
| Part Number | ADSP-BF561SKBCZ500 | |
| Description | Blackfin Embedded Symmetric Multi-Processor | |
| Manufacturers | Analog Devices | |
| Logo |  |
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There is a preview and ADSP-BF561SKBCZ500 download ( pdf file ) link at the bottom of this page. Total 30 Pages | ||
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a
Preliminary Technical Data
FEATURES
Dual Symmetric 600 Mhz High Performance Blackfin Core
328 KBytes of On-chip Memory (See Memory Info on Page 3)
Each Blackfin Core Includes:
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,
40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of Pro-
gramming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance- Monitoring
0.8 - 1.2V core VDD with On-Chip Voltage Regulation
3.3V and 2.5V Tolerant I/O
256-Ball Mini BGA and 297-Ball PBGA Package Options
Blackfin® Embedded
Symmetric Multi-Processor
ADSP-BF561
PERIPHERALS
Two Parallel Input/Output Peripheral Interface Units Sup-
porting ITU-R 656 Video and Glueless Interface to ADI
Analog Front End ADCs
Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-
porting Eight Stereo I2S Channels
Dual 16 Channel DMA Controllers and one internal memory
DMA controller
12 General Purpose 32-bit Timer/Counters, with PWM
Capability
SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
48 Programable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency
Multiplication
IRQ CTRL/
TIMER
VOLTAGE
REGULATOR
B
B
IRQ CTRL/
TIMER
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L2 SRAM
128 KBYTES
CORE SYSTEM / BUS INTERFACE
EAB
32
BOOT ROM
DMA
CONTROLLER1
DMA
CONTROLLER2
32
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI PPI
IMDMA
CONTROLLER
DAB
PAB 16
16
JTAG TEST
EMULATION
UART
IRDA®
SPI
SPORT0
SPORT1
GPIO
TIMERS
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
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Preliminary Technical Data
ADSP-BF561
0xFFFFFFFF
0xFFE0 0000
0xFFC00000
0xFFB01000
0xFFB00000
0xFFA14000
0xFFA10000
0xFFA04000
0xFFA00000
0xFF908000
0xFF904000
0xFF900000
0xFF808000
0xFF804000
0xFF800000
0xFEB2 0000
0xFEB0 0000
0xEF00 4000
0xEF00 0000
0x3000 0000
0x2C00 0000
0x2800 0000
0x2400 0000
0x2000 0000
Topof last SDRAMpage
0x0000 0000
COREAMEMORYMAP
COREBMEMORYMAP
COREMMRREGISTERS
COREMMRREGISTERS
SYSTEMMMRREGISTERS
RESERVED
L1SCRATCHPADSRAM(4K)
RESERVED
L1INSTRUCTIONSRAM/CACHE(16K)
RESERVED
L1INSTRUCTIONSRAM(16K)
RESERVED
RESERVED
L1DATABANKBSRAM/CACHE(16K)
L1DATABANKBSRAM(16K)
RESERVED
L1DATABANKASRAM/CACHE(16K)
L1DATABANKASRAM(16K)
RESERVED
RESERVED
L1 SCRATCHPADSRAM(4K)
RESERVED
L1 INSTRUCTIONSRAM/CACHE(16K)
RESERVED
L1 INSTRUCTIONSRAM(16K)
RESERVED
L1DATABANKBSRAM/CACHE(16K)
L1 DATABANKBSRAM(16K)
RESERVED
L1DATABANKASRAM/CACHE(16K)
L1 DATABANKASRAM(16K)
RESERVED
L2 SRAM(128K)
RESERVED
BOOTROM
RESERVED
ASYNCMEMORYBANK3
ASYNCMEMORYBANK2
ASYNCMEMORYBANK1
ASYNCMEMORYBANK0
RESERVED
SDRAMBANK3
SDRAMBANK2
SDRAMBANK1
SDRAMBANK0
0xFF800000
0xFF701000
0xFF700000
0xFF614000
0xFF610000
0xFF604000
0xFF600000
0xFF508000
0xFF504000
0xFF500000
0xFF408000
0xFF404000
0xFF400000
INTERNALMEMORY
EXTERNALMEMORY
Figure 3. Memory Map
The fourth on-chip memory system is the L2 SRAM memory
array which provides 128K bytes of high speed SRAM operating
at one half the bandwidth of the core, and slightly longer latency
than the L1 memory banks. The L2 memory is a unified instruc-
tion and data memory and can hold any mixture of code and
data required by the system design. The Blackfin cores share a
dedicated low-latency 64-bit wide data path port into the L2
SRAM memory.
Each Blackfin core processor has its own set of core Memory
Mapped Registers (MMRs) but share the same system MMR
registers and 128 KB L2 SRAM memory.
External (Off-Chip) Memory
The ADSP-BF561 external memory is accessed via the External
Bus Interface Unit (EBIU). This interface provides a glueless
connection to up to four banks of synchronous DRAM
(SDRAM) as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
The PC133-compliant SDRAM controller can be programmed
to interface to up to four banks of SDRAM, with each bank con-
taining between 16M bytes and 128M bytes providing access to
up to 512M bytes of SDRAM. Each bank is independently pro-
grammable and is contiguous with adjacent banks regardless of
the sizes of the different banks or their placement. This allows
flexible configuration and upgradability of system memory
while allowing the core to view all SDRAM as a single, contigu-
ous, physical address space.
The asynchronous memory controller can also be programmed
to control up to four banks of devices with very flexible timing
parameters for a wide variety of devices. Each bank occupies a
Rev. PrC | Page 5 of 52 | April 2004
Preview 5 Page |
Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for ADSP-BF561SKBCZ500 electronic component. |
| Information | Total 30 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ ADSP-BF561SKBCZ500.PDF Datasheet ] | |
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