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ADSP-BF561SBB500 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-BF561SBB500
Beschreibung Blackfin Embedded Symmetric Multi-Processor
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-BF561SBB500 Datasheet, Funktion
a
Preliminary Technical Data
FEATURES
Dual Symmetric 600 Mhz High Performance Blackfin Core
328 KBytes of On-chip Memory (See Memory Info on Page 3)
Each Blackfin Core Includes:
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,
40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of Pro-
gramming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance- Monitoring
0.8 - 1.2V core VDD with On-Chip Voltage Regulation
3.3V and 2.5V Tolerant I/O
256-Ball Mini BGA and 297-Ball PBGA Package Options
Blackfin® Embedded
Symmetric Multi-Processor
ADSP-BF561
PERIPHERALS
Two Parallel Input/Output Peripheral Interface Units Sup-
porting ITU-R 656 Video and Glueless Interface to ADI
Analog Front End ADCs
Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-
porting Eight Stereo I2S Channels
Dual 16 Channel DMA Controllers and one internal memory
DMA controller
12 General Purpose 32-bit Timer/Counters, with PWM
Capability
SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
48 Programable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency
Multiplication
IRQ CTRL/
TIMER
VOLTAGE
REGULATOR
B
B
IRQ CTRL/
TIMER
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L1
INSTRUCTION
MEMORY
MMU
L1
DATA
MEMORY
L2 SRAM
128 KBYTES
CORE SYSTEM / BUS INTERFACE
EAB
32
BOOT ROM
DMA
CONTROLLER1
DMA
CONTROLLER2
32
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI PPI
IMDMA
CONTROLLER
DAB
PAB 16
16
JTAG TEST
EMULATION
UART
IRDA®
SPI
SPORT0
SPORT1
GPIO
TIMERS
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.






ADSP-BF561SBB500 Datasheet, Funktion
ADSP-BF561
64M-byte segment regardless of the size of the devices used so
that these banks will only be contiguous if fully populated with
64M bytes of memory.
I/O Memory Space
Blackfin processors do not define a separate I/O space. All
resources are mapped through the flat 32-bit address space. On-
chip I/O devices have their control registers mapped into mem-
ory-mapped registers (MMRs) at addresses near the top of the
4G-byte address space. These are separated into two smaller
blocks, one which contains the control MMRs for all core func-
tions, and the other which contains the registers needed for
setup and control of the on-chip peripherals outside of the core.
The core MMRs are accessible only by the core and only in
supervisor mode and appear as reserved space by on-chip
peripherals. The system MMRs are accessible by the core in
supervisor mode and can be mapped as either visible or reserved
to other devices, depending on the system protection model
desired.
Booting
The ADSP-BF561 contains a small boot kernel, which config-
ures the appropriate peripheral for booting. If the ADSP-BF561
is configured to boot from boot ROM memory space, the pro-
cessor starts executing from the on-chip boot ROM.
Event Handling
The event controller on the ADSP-BF561 handles all asynchro-
nous and synchronous events to the processor. The ADSP-
BF561 provides event handling that supports both nesting and
prioritization. Nesting allows multiple event service routines to
be active simultaneously. Prioritization ensures that servicing of
a higher-priority event takes precedence over servicing of a
lower-priority event. The controller provides support for five
different types of events:
• Emulation – An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset – This event resets the processor.
• Non-Maskable Interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut
down of the system.
• Exceptions – Events that occur synchronously to program
flow, i.e., the exception will be taken before the instruction
is allowed to complete. Conditions such as data alignment
violations, undefined instructions, etc. cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by timers, peripherals, input pins,
and an explicit software instruction.
Each event has an associated register to hold the return address
and an associated return-from-event instruction. When an
event is triggered, the state of the processor is saved on the
supervisor stack.
Preliminary Technical Data
The ADSP-BF561 event controller consists of two stages, the
Core Event Controller (CEC) and the System Interrupt Control-
ler (SIC). The Core Event Controller works with the System
Interrupt Controller to prioritize and control all system events.
Conceptually, interrupts from the peripherals enter into the
SIC, and are then routed directly into the general-purpose inter-
rupts of the CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF561. Table 1 describes
the inputs to the CEC, identifies their names in the Event Vector
Table (EVT), and lists their priorities.
Table 1. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test
Reset
Non-Maskable
Exceptions
Global Enable
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
-
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
System Interrupt Controller (SIC)
The System Interrupt Controller provides the mapping and
routing of events from the many peripheral interrupt sources, to
the prioritized general-purpose interrupt inputs of the CEC.
Although the ADSP-BF561 provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the Interrupt Assignment
Registers (IAR). Table 2 describes the inputs into the SIC and
the default mappings into the CEC.
Rev. PrC | Page 6 of 52 | April 2004

6 Page









ADSP-BF561SBB500 pdf, datenblatt
ADSP-BF561
the processor can take advantage of Dynamic Power Manage-
ment, without affecting the I/O devices. There are no
sequencing requirements for the various power domains.
Table 4. ADSP-BF561 Power Domains
Power Domain
All internal logic
I/O
VDD Range
VDDINT
VDDEXT
The power dissipated by a processor is largely a function of the
clock frequency of the processor and the square of the operating
voltage. For example, reducing the clock frequency by 25%
results in a 25% reduction in dynamic power dissipation, while
reducing the voltage by 25% reduces dynamic power dissipation
by more than 40%. Further, these power savings are additive, in
that if the clock frequency and supply voltage are both reduced,
the power savings can be dramatic.
The Dynamic Power Management feature of the ADSP-BF561
allows both the processor’s input voltage (VDDINT) and clock
frequency (fCCLK) to be dynamically controlled.
The savings in power dissipation can be modeled using the
Power Savings Factor and % Power Savings calculations.
Preliminary Technical Data
The Power Savings Factor is calculated as:
Power Savings Factor
=
-f--C---C---L--K---R--E---D--
fCCLKNOM
×
V-V----D-D--D-D--I-IN-N--T-T--N-R--OE---DM--⎠⎞
2
×
-T----R---E--D--
TNOM
where the variables in the equations are:
• fCCLKNOM is the nominal core clock frequency
• fCCLKRED is the reduced core clock frequency
• VDDINTNOM is the nominal internal supply voltage
• VDDINTRED is the reduced internal supply voltage
• TNOM is the duration running at fCCLKNOM
• TRED is the duration running at fCCLKRED
The percent power savings is calculated as:
% Power Savings = (1 – Power Savings Factor) × 100%
VOLTAGE REGULATION
The ADSP-BF561 processor provides an on-chip voltage regula-
tor that can generate processor core voltage levels 0.85V(-5% /
+10%) to 1.2V(-5% / +10%) from an external 2.25 V to 3.6 V
supply. Figure 4 shows the typical external components
required to complete the power management system. The regu-
lator controls the internal logic voltage levels and is
programmable with the Voltage Regulator Control Register
(VR_CTL) in increments of 50 mV. To reduce standby power
consumption, the internal voltage regulator can be programmed
to remove power to the processor core while keeping I/O power
(VDDEXT) supplied. While in hibernation, VDDEXT can still be
applied, eliminating the need for external buffers. The voltage
regulator can be activated from this powerdown state by assert-
ing RESET, which will then initiate a boot sequence. The
regulator can also be disabled and bypassed at the user’s
discretion.
Figure 4. Voltage Regulator Circuit
Rev. PrC | Page 12 of 52 | April 2004

12 Page





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