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PDF ADSP-21msp59 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21msp59 | |
| Descripción | DSP Microcomputers | |
| Fabricantes | Analog Devices | |
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FEATURES
38 ns Instruction Cycle Time (26 MIPS) from 13.00 MHz
Crystal
ADSP-2100 Family Code and Function Compatible with
New Instruction Set Enhanced for Bit Manipulation
Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
2K ؋ 24 Words of On-Chip Program Memory RAM
2K ؋ 16 Words of On-Chip Data Memory RAM
4K ؋ 24 Words of On-Chip Program Memory ROM
(ADSP-21msp59 Only)
8-Bit Parallel Host Interface Port
Analog Interface Provides:
16-Bit Sigma-Delta ADC and DAC
Programmable Gain Stages
On-Chip Anti-Aliasing & Anti-Imaging Filters
8 kHz Sampling Frequency
65 dB ADC, SNR and THD
72 dB DAC, SNR and THD
425 mW Typical Power Dissipation @ 5.0 V @ 38 ns
<1 mW Powerdown Mode with 100 Cycle Recovery
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides:
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware, One Serial Port (SPORT0) has Automatic
Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (ADSP-21msp59 Only)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
100-Lead TQFP
DSP Microcomputers
ADSP-21msp58/59
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY
ADSP-21msp59
ADSP-21msp58/59
PROGRAM
MEMORY
4K x 24
(ROM)
PROGRAM DATA
MEMORY MEMORY
2K x 24
2K x 16
POWERDOWN
CONTROL
LOGIC
FLAG
ANALOG
INTERFACE
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
TIMER
SERIAL PORTS
SPORT 0 SPORT 1
HOST
INTERFACE
PORT
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
GENERAL DESCRIPTION
The ADSP-21msp58 and ADSP-21msp59 Mixed-Signal Pro-
cessors (MSProcessor® DSPs) are fully integrated, single-chip
DSPs complete with a high performance analog front end. The
ADSP-21msp58/59 Family is optimized for voice band applica-
tions such as Speech Compression, Speech Processing, Speech
Recognition, Text-to Speech, and Speech-to-Text conversion.
The ADSP-21msp58/59 combines the ADSP-2100 base archi-
tecture (three computation units, data address generators, and
program sequencer) with two serial ports, a host interface port,
an analog front end, a programmable timer, extensive interrupt
capability, and on-chip program and data memory.
The ADSP-21msp58 provides 2K words (24-bit) of program
RAM and 2K words (16-bit) of data memory. The ADSP-
21msp59 provides an additional 4K words (24-bit) of program
ROM. The ADSP-21msp58/59 integrates a high performance
analog codec based on a single chip, voice band codec, the
AD28msp02. Powerdown circuitry is also provided to meet the
low power needs of battery operated portable equipment. The
ADSP-21msp58/59 is available in a 100-pin TQFP package
(thin quad flat package).
In addition, the ADSP-21msp58/59 supports new instructions,
which include bit manipulations–bit set, bit clear, bit toggle,
bit test–new ALU constants, new multiplication instruction
(x squared), biased rounding, and global interrupt masking.
MSProcessor is a registered trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
ADSP-21msp58/59
ICNTL
4 3210
0
IMASK
98765 4 3210
0000000000
IRQ0 Sensitivity
IRQ1 Sensitivity
IRQ2 Sensitivity
1 = edge
0 = level
Interrupt Nesting
1 = enable, 0 = disable
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
IFC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Timer
IRQ0 or SPORT1 Receive
IRQ1 or SPORT1 Transmit
Analog Receive
Analog Transmit
1 = enable, 0 = disable
INTERRUPT FORCE
IRQ2
SPORT0 Transmit
SPORT0 Receive
Analog Transmit
Analog Receive
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
INTERRUPT CLEAR
Timer
SPORT1 Receive or IRQ0
SPORT1 Transmit or IRQ1
Analog Receive
Analog Transmit
SPORT0 Receive
SPORT0 Transmit
IRQ2
1 = enable, 0 = disable
Figure 2. Interrupt Registers
Table II. Interrupt Priority & Interrupt Vector Addresses
Source of Interrupt
Interrupt Vector
Address (Hex)
Reset (or Power-Up with PUCR = 1)
Powerdown (Nonmaskable)
IRQ2
HIP Write
HIP Read
SPORT0 Transmit
SPORT0 Receive
Analog Interface Transmit
Analog Interface Receive
SPORT1 Transmit or (IRQ1)
SPORT1 Receive or (IRQ0)
Timer
0000 (Highest Priority)
002C
0004
0008
000C
0010
0014
0018
001C
0020
0024
0028 (Lowest Priority)
Interrupts can be masked or unmasked with the IMASK regis-
ter. Individual interrupt requests are logically ANDed with the
bits in IMASK; the highest priority unmasked interrupt is then
selected. The powerdown interrupt is non-maskable.
The interrupt control register, ICNTL, allows the external in-
terrupts to be set as either edge- or level-sensitive. Interrupt ser-
vice routines can either be nested (with higher priority interrupts
taking precedence) or be processed sequentially (with only one
interrupt service active at a time).
The interrupt force and clear register, IFC, is a write-only regis-
ter used to force an interrupt or clear a pending edge-sensitive
interrupt.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stack is twelve
levels deep to allow interrupt nesting.
Register bit values shown in Figure 2 are the default bit values
after reset. If no values are shown, the bits are indeterminate at
reset. Reserved bits are shown in gray; these bits should always
be written with zeros.
The following instructions allow global enable or disable servic-
ing of the interrupts (including powerdown), regardless of the
state of IMASK. Disabling the interrupts does not affect
autobuffering.
ENA INTS;
DIS INTS;
Interrupt servicing is enabled on processor reset.
System Interface
Figure 3 shows a basic system configuration with the ADSP-
21msp58/59, two serial devices, a host processor, a boot
EPROM, optional external program and data memories, and an
analog interface. Up to 15K words of data memory and 16K
words of program memory can be supported. Programmable
wait state generation allows the processor to interface easily to
slow memories. The ADSP-21msp58/59 also provides one ex-
ternal interrupt and two serial ports or three external interrupts
and one serial port.
Clock Signals
The ADSP-21msp58/59 CLKIN input may be driven by a crys-
tal or by a TTL-compatible external clock signal.
The CLKIN input may not be halted, changed in frequency
during operation, or operated at any frequency other the one
specified. Operating the ADSP-21msp58/59 at any other fre-
quency changes the analog performance, which is not tested or
supported.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal should be
connected to the processor’s CLKIN input; in this case, the
XTAL input must be left unconnected.
The ADSP-21msp58/59 uses an input clock with a frequency
equal to half the instruction rate; a 13 MHz input clock yields a
38.46 ns processor cycle (which is equivalent to 26 MHz). Nor-
mally, instructions are executed in a single processor cycle.
All device timing is relative to the internal instruction clock rate,
which is indicated by the CLKOUT signal when enabled. The
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5 Page 
ADSP-21msp58/59
Autobuffering
In some applications, it is advantageous to perform block data
transfers between the analog converters and processor memory.
Analog interface autobuffering enables the automatic transfer of
data blocks directly from the ADC to on-chip processor data
memory or from on-chip processor data memory directly to the
DAC.
ADC and DAC Interrupts
The analog interface generates two interrupts that signal either:
(1) a 16-bit, 8 kHz analog-to-digital or digital-to-analog conver-
sion has been completed, or (2) an autobuffer block transfer
has been completed (i.e., the data buffer contents have been
received or transferred).
When an analog interrupt occurs, the processor vectors to the
addresses listed in Table II, Interrupt Priority & Interrupt Vector
Addresses.
The ADC receive and DAC transmit interrupts occur at an
8 kHz rate, indicating when the data registers should be ac-
cessed. On the receive side, the ADC interrupt is generated each
time an A/D conversion cycle is completed and the 16-bit data
word is available in the ADC receive register. On the transmit
side, the DAC interrupt is generated each time an D/A conver-
sion cycle is completed and the DAC transmit register is ready
for the next 16-bit data word.
Both interrupts are generated simultaneously at an 8 kHz rate,
occurring every 3250 instruction cycles with a 13 MHz internal
processor clock. The interrupts are generated continuously,
starting when the analog interface is powered up by setting the
APWD bits (Bits 5 and 6) to one in the analog control register.
Because both interrupts occur simultaneously, only one should
be enabled (in IMASK) to vector to a single service routine that
handles transmit and receive data. However, when using
autobuffer transfers, both interrupts should be enabled.
ADSP-21msp58/59 REGISTERS
Figure 9 summarizes the ADSP-21msp58/59 registers. Some
registers store values. For example, AX0 stores an ALU oper-
and; I4 stores a DAG2 pointer. Other registers consist of control
bits and fields, or status flags. For example ASTAT contains
status flags from arithmetic operations, and fields in DWAIT
control the number of wait states for different zones of data
memory.
A secondary set of registers in all computational units allows a
single-cycle context switch.
The bit and field definitions for control and status registers are
given in the rest of this section, except IMASK, ICNTL, and
IFC, which are defined earlier in this data sheet. The system
control register, DWAIT register, timer registers, HIP control
registers, HIP data registers, and SPORT control registers are
all mapped into data memory locations; that is, you access these
registers by reading and writing data memory locations rather
than register names. The particular data memory address is
shown with each memory-mapped register.
Register bit values shown on the following pages are the default
bit values after reset. If no values are shown, the bits are indeter-
minate at reset. Reserved bits are shown in gray; these bits
should always be written with zeros.
DAG 1
I0 M0 L0
I1 M1 L1
I2 M2 L2
I3 M3 L3
DAG 2
I4 M4 L4
I5 M5 L5
I6 M6 L6
I7 M7 L7
PROGRAM SEQUENCER
SSTAT
CNTR
OWRCNTR
COUNT
STACK
4 x 14
ICNTL
IFC
IMASK
MSTAT
ASTAT
STATUS
STACK
12 x 25
LOOP
STACK
4 x 18
PC
STACK
16 x 14
0x3FFF SYSTEM CONTROL
0x3FFE DM WAIT CONTROL
14 PMA BUS
PROGRAM
SRAM
2K x 24
PROGRAM
ROM
4K x 24
ADSP-21msp59
ONLY
DATA
SRAM
2K x 16
14 DMA BUS
24 PMD BUS
16 DMD BUS
PX
HOST
INTERFACE
PORT
0x3FE0-0x3FE5 DATA
0x3FE6-0x3FE7 STATUS
0x3FE8
HMASK
AX0 AX1 AY0 AY1
ALU
AR AF
MX0 MX1 MY0 MY1
MAC
MR0 MR1 MR2 MF
SI SE SB
SHIFTER
SR0 SR1
0x3FEC 0x3FED
DAC
ADC
0x3FEE-0x3FEF
CONTROL REGISTERS
ANALOG INTERFACE
RX0 TX0
0x3FFA-0x3FF3
CONTROL REGISTERS
SPORT 0
RX1 TX1
0x3FF2-0x3FEF
CONTROL REGISTERS
SPORT 1
TIMER
0x3FFD TPERIOD
0x3FFC TCOUNT
0x3FFB TSCALE
FLAG
POWERDOWN
CONTROL
LOGIC
Figure 9. ADSP-21msp58/59 Registers
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| PDF Descargar | [ Datasheet ADSP-21msp59.PDF ] | |
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