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PDF ADSP-21MOD980N Data sheet ( Hoja de datos )
| Número de pieza | ADSP-21MOD980N | |
| Descripción | MultiPort Internet Gateway Processor | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Preliminary Technical Data
MultiPort Internet
Gateway Processor
ADSP-21mod980N
PERFORMANCE FEATURES
Complete Single Device Multi-Port Internet Gateway
Processor (No External Memory Required)
Implements Sixteen Modem Channels or Forty Voice
Channels in One Package
Each DSP Can Implement two V.34/V.90 Data/Fax
Modem Channels (includes Datapump and
Controller)
Low Power Version: 640 MIPS Sustained Performance,
12.5 ns Instruction Time @ 1.9 Volts nominal
(internal)
Open Architecture Extensible to Voice-over-Network
(VoN) and Other Applications
Low Power Dissipation, 25 mW (typical) per Channel
Powerdown Mode Featuring Low CMOS Standby Power
Dissipation
INTEGRATION FEATURES
ADSP-2100 Family Code-Compatible, with Instruction
Set Extensions
16 Mbits of On-Chip SRAM, Configured as 9 Mbits of
Program Memory and 7 Mbits of Data Memory
Dual-Purpose Program Memory, for Both Instruction
and Data Storage
352-Ball PBGA with a 35mm ؋ 35mm footprint
SYSTEM CONFIGURATION FEATURES
16-Bit Internal DMA Port for High-Speed Access to
On-Chip Memory (Mode-Selectable)
Programmable Multichannel Serial Port Supports 24/32
Channels
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Separate Reset Pins for Each Internal Processor
Host IDMA
SPORT0
SPORT1
21mod980N
2188N
DSP 1
2188N
DSP 2
2188N
DSP 3
2188N
DSP 4
2188N
DSP 5
2188N
DSP 6
2188N
DSP 7
2188N
DSP 8
CONTROL
Figure 1. MOD980N MultiPort Internet Gateway Processor Block Diagram
REV. PrB 6/2001
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2001
1 page  
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
All eight modem processors have identical functions and
have equal status. Each of the modem processors is con-
nected to a common IDMA bus and each modem processor
is configured to operate in the same mode (see the slave
mode and the memory mode descriptions in “Memory
Architecture” on page 10). The slave mode is considered to
be the only mode of operation in the ADSP-21mod980N
modem pool.
SERIAL PORTS
The ADSP-21mod980N has a multichannel serial port
(SPORT) connected to each internal digital modem pro-
cessor for serial communications.
The following is a brief list of ADSP-21mod980N SPORT
features. For additional information on the internal Serial
Ports, refer to the ADSP-2100 Family User’s Manual. Each
SPORT:
• is bidirectional and has a separate, double-buffered
transmit and receive section.
• can use an external serial clock or generate its own
serial clock internally.
• has independent framing for the receive and transmit
sections. Sections run in a frameless mode or with
frame synchronization signals internally or externally
generated. Frame sync signals are active high or
inverted, with either of two pulse widths and timings.
• supports serial data word lengths from 3 to 16 bits and
provides optional A-law and µ-law companding accord-
ing to CCITT recommendation G.711.
• receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• can receive and transmit an entire circular buffer of
data with one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
A multichannel interface selectively receives and transmits a
24 or 32 word, time-division multiplexed, serial bitstream.
PIN DESCRIPTIONS
The ADSP-21mod980N is available in a 352-lead PBGA
package. In order to maintain maximum functionality and
reduce package size and pin count, some serial port, pro-
grammable flag, interrupt and external bus pins have dual,
multiplexed functionality. The external bus pins are config-
ured during RESET only, while serial port pins are software
configurable during program execution. Flag and interrupt
functionality is retained concurrently on multiplexed pins.
Table on page 6 lists the pin names and their functions. In
cases where pin functionality is reconfigurable, the default
state is shown in plain text; alternate functionality is shown
in italics.
ADSP-21mod980N
REV. PrB 6/2001
5
5 Page 
PRELIMINARY TECHNICAL DATA
For current information contact Analog Devices at (800) ANALOGD
ADSP-21mod980N
DATA MEMORY
ALWAYS
A C C E SS IB L E
AT ADDRESS
0x2000 - 0x3FFF
0x0000 - 0x1FFF
0x0000 - 0x1FFF
ACCESSIBLE W HEN
DM OVLAY = 0
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 4
0x0000 - 0x1FFF
ACCESSIBLE W HEN
DM OVLAY = 5
0x0000 - 0x1FFF
IN TER NA L
MEMORY
ACCESSIBLE W HEN
DM OVLAY = 6
ACCESSIBLE W HEN
DM OVLAY = 7
0x0000 - 0x1FFF
ACCESSIBLE WHEN
DM OVLAY = 8
Table 5. DMOVLAY bits
DMOVLAY Memory A13
0, 4, 5, 6, 7, 8 Internal Not
Applicable
A[12:0]
Not
Applicable
MEMORY MAPPED REGISTERS (NEW TO THE
ADSP-21MOD980N)
The ADSP-21mod980N has three memory mapped regis-
ters that differ from other ADSP-21xx Family DSPs. See
“Waitstate Control Register” on page 11. See
“Programmable Flag & Composite Select Control Regis-
ter” on page 12. See “System Control Register” on
page 12. The slight modifications to these registers provide
the ADSP-21mod980N’s waitstate and BMS control
features.
DATA MEMORY
32 MEMORY
MAPPED
REGISTERS
INTERNAL
8160 WORDS
8K INTERNAL
DMOVLAY =
0, 4, 5, 6, 7, 8
ADDR
0x3FFF
0x3FE0
0x3FDF
0x2000
0x1FFF
Figure 5. Data Memory Map
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
11111111
11
1 1 1 1 1 1 DM (0x3FFE)
.
D W A IT
IOW AIT 3
IOW AIT 2
IOW AIT 1
IOW AIT 0
Wait State Mode Select
0 = Normal mode (PWAIT, DWAIT, IOWAIT0-3 = N wait states, ranging from 0 to 7)
1 = 2N+1 mode (PWAIT, DWAIT, IOWAIT0-3 = 2N+1 wait states, ranging from 0 to 15)
Figure 6. Waitstate Control Register
REV. PrB 6/2001
11
11 Page | ||
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