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ADSP-2195MKST-160X Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2195MKST-160X
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-2195MKST-160X Datasheet, Funktion
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a
Preliminary Technical Data
DSP Microcomputer
ADSP-2195
ADSP-219x DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy -to-Use Algebraic Syntax
Single-Cycle Instruction Execution
Up to 16M words of Addressable Memory Space with
24 Bits of Addressing Width
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code
Execution at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C
Code Efficiency
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This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2001






ADSP-2195MKST-160X Datasheet, Funktion
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2195
For current information contact Analog Devices at 800/262-5643
September 2001
a peripheral to one of the 12 user-defined interrupts. These
assignments determine the priority of each peripheral for
interrupt service.
There are three serial ports on the ADSP-2195 that provide
a complete synchronous, full-duplex serial interface. This
interface includes optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation. Each serial port can transmit or receive
an internal or external, programmable serial clock and
frame syncs. Each serial port supports 128-channel Time
Division Multiplexing.
The ADSP-2195 provides up to sixteen general-purpose
I/O pins, which are programmable as either inputs or
outputs. Eight of these pins are dedicated general purpose
Programmable Flag pins. The other eight of them are mul-
tifunctional pins, acting as general purpose I/O pins when
the DSP connects to an 8-bit external data bus and acting
as the upper eight data pins when the DSP connects to a
16-bit external data bus. These Programmable Flag pins can
implement edge- or level-sensitive interrupts, some of which
can be used to base the execution of conditional
instructions.
Three programmable interval timers generate periodic
interrupts. Each timer can be independently set to operate
in one of three modes:
• Pulse Waveform Generation mode
• Pulsewidth Count/Capture mode
• External Event Watchdog mode
Each timer has one bi-directional pin and four registers that
implement its mode of operation: A 7-bit configuration
register, a 32-bit count register, a 32-bit period register, and
a 32-bit pulsewidth register. A single status register supports
all three timers. A bit in the mode status register globally
enables or disables all three timers, and a bit in each timer’s
configuration register enables or disables the corresponding
timer independently of the others.
Memory Architecture
The ADSP-2195 DSP provides 32K words of on-chip
SRAM memory. This memory is divided into two 16K
blocks located on memory Page 0 in the DSP’s memory
map. The DSP also provides 16K words of on-chip ROM.
In addition to the internal and external memory space, the
ADSP-2195 can address two additional and separate
off-chip memory spaces: I/O space and boot space.
As shown in Figure 2, the DSP’s two internal memory
blocks populate all of Page 0. The entire DSP memory map
consists of 256 pages (Pages 0255), and each page is 64K
words long. External memory space consists of four
memory banks (banks 0–3) and supports a wide variety of
SRAM memory devices. Each bank is selectable using the
memory select pins (MS3–0) and has configurable page
boundaries, waitstates, and waitstate modes. The 1K word
of on-chip boot-ROM populates the top of Page 255 while
the remaining 254 pages are addressable off-chip. I/O
memory pages differ from external memory pages in that
I/O pages are 1K word long, and the external I/O pages have
their own select pin (IOMS). Pages 0–31 of I/O memory
space reside on-chip and contain the configuration registers
for the peripherals. Both the ADSP-2195 and DMA-capa-
ble peripherals can access the DSP’s entire memory map.
Internal (On-Chip) Memory
The ADSP-2195’s unified program and data memory space
consists of 16M locations that are accessible through two
24-bit address buses, the PMA and DMA buses. The DSP
uses slightly different mechanisms to generate a 24-bit
address for each bus. The DSP has three functions that
support access to the full memory map.
• The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.
• The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
• For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
The ADSP-2195 has 1K word of on-chip ROM that holds
boot routines. If peripheral booting is selected, the DSP
starts executing instructions from the on-chip boot ROM,
which starts the boot process from the selected peripheral.
For more information, see Booting Modes on page 15. The
on-chip boot ROM is located on Page 255 in the DSP’s
memory space map.
Internal On-Chip ROM
The ADSP-2195 DSP features a 16K-word × 24-bit
on-chip maskable ROM mapped into program memory
space (Figure 3).
Customers can arrange to have the ROM programmed with
application-specific code.
6
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

6 Page









ADSP-2195MKST-160X pdf, datenblatt
35(/,0,1$5< 7(&+1,&$/ '$7$
ADSP-2195
For current information contact Analog Devices at 800/262-5643
September 2001
During transfers, the SPI ports simultaneously transmit and
receive by serially shifting data in and out on their two serial
data lines. The serial clock line synchronizes the shifting and
sampling of data on the two serial data lines.
In master mode, the DSP’s core performs the following
sequence to set up and initiate SPI transfers:
1. Enables and configures the SPI port’s operation (data
size, and transfer format).
2. Selects the target SPI slave with an SPIxSELy output
pin (reconfigured Programmable Flag pin).
3. Defines one or more DMA descriptors in Page 0 of I/O
memory space (optional in DMA mode only).
4. Enables the SPI DMA engine and specifies transfer
direction (optional in DMA mode only).
5. In non-DMA mode only, reads or writes the SPI port
receive or transmit data buffer.
The SCKx line generates the programmed clock pulses
for simultaneously shifting data out on MOSIx and
shifting data in on MISOx. In DMA mode only, transfers
continue until the SPI DMA word count transitions
from 1 to 0.
In slave mode, the DSP’s core performs the following
sequence to set up the SPI port to receive data from a master
transmitter:
1. Enables and configures the SPI slave port to match the
operation parameters set up on the master (data size
and transfer format) SPI transmitter.
2. Defines and generates a receive DMA descriptor in
Page 0 of memory space to interrupt at the end of the
data transfer (optional in DMA mode only).
3. Enables the SPI DMA engine for a receive access
(optional in DMA mode only).
4. Starts receiving the data on the appropriate SPI SCKx
edges after receiving an SPI chip select on an SPISSx
input pin (reconfigured Programmable Flag pin)
from a master
In DMA mode only, reception continues until the SPI
DMA word count transitions from 1 to 0. The DSP’s core
could continue, by queuing up the next DMA descriptor.
A slave mode transmit operation is similar, except the DSP’s
core specifies the data buffer in memory space from which
to transmit data, generates and relinquishes control of the
transmit DMA descriptor, and begins filling the SPI port’s
data buffer. If the SPI controller isn’t ready on time to
transmit, it can transmit a “zero” word.
include support for 5–8 data bits; 1 or 2 stop bits; and none,
even, or odd parity. The UART port supports two modes
of operation:
• PIO (programmed I/O)
The DSP’s core sends or receives data by writing or
reading I/O-mapped UATX or UARX registers, respec-
tively. The data is double-buffered on both transmit and
receive.
• DMA (direct memory access)
The DMA controller transfers both transmit and receive
data. This reduces the number and frequency of inter-
rupts required to transfer data to and from memory. The
UART has two dedicated DMA channels. These DMA
channels have lower priority than most DMA channels
because of their relatively low service rates.
The UART’s baud rate (see Figure 5), serial data format,
error code generation and status, and interrupts are
programmable:
• Supported bit rates range from 95 bits to 6.25M bits per
second (100 MHz peripheral clock).
• Supported data formats are 7- or 12-bit frames.
• Transmit and receive status can be configured to generate
maskable interrupts to the DSP’s core.
UART Clock Rate = H-1---6--C---×-L----D-K---
Figure 5. UART Clock Rate Calculation1
1Where D = 1 to 65536
The timers can be used to provide a hardware-assisted
autobaud detection mechanism for the UART interface.
Programmable Flag (PFx) Pins
The ADSP-2195 has 16 bidirectional, general-purpose I/O,
Programmable Flag (PF15–0) pins. The PF7–0 pins are
dedicated to general-purpose I/O. The PF15–8 pins serve
either as general-purpose I/O pins (if the DSP is connected
to an 8-bit external data bus) or serve as DATA15–8 lines
(if the DSP is connected to a 16-bit external data bus). The
Programmable Flag pins have special functions for clock
multiplier selection and for SPI port operation. For more
information, see Serial Peripheral Interface (SPI) Ports on
UART Port
The UART port provides a simplified UART interface to
another peripheral or Host. It performs full duplex, asyn-
chronous transfers of serial data. Options for the UART
12
This information applies to a product under development. Its characteristics and specifications are subject to change with-
REV. PrA
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

12 Page





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