ADSP-2195MKCA-160X Datasheet PDF - Analog Devices
| Part Number | ADSP-2195MKCA-160X | |
| Description | DSP Microcomputer | |
| Manufacturers | Analog Devices | |
| Logo |  |
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Preliminary Technical Data
DSP Microcomputer
ADSP-2195
ADSP-219x DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy -to-Use Algebraic Syntax
Single-Cycle Instruction Execution
Up to 16M words of Addressable Memory Space with
24 Bits of Addressing Width
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code
Execution at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C
Code Efficiency
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FUNCTIONAL BLOCK DIAGRAM
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This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700 World Wide Web Site: http://www.analog.com
Fax:781/326-8703
©Analog Devices,Inc., 2001
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September 2001 For current information contact Analog Devices at 800/262-5643
ADSP-2195
within 64K word boundaries of each of the 256 memory
pages, but these buffers may not cross page boundaries.
Secondary registers duplicate all the primary registers in the
DAGs; switching between primary and secondary registers
provides a fast context switch.
Efficient data transfer in the core is achieved with the use of
internal buses:
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• DMA Address Bus
• DMA Data Bus
The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded
off-chip, and the two data buses (PMD and DMD) share a
single external data bus. Boot memory space and I/O
memory space also share the external buses.
Program memory can store both instructions and data, per-
mitting the ADSP-2195 to fetch two operands in a single
cycle, one from program memory and one from data
memory. The DSP’s dual memory buses also let the
ADSP-219x core fetch an operand from data memory and
the next instruction from program memory in a single cycle.
DSP Peripherals Architecture
The functional block diagram on page 1 shows the DSP’s
on-chip peripherals, which include the external memory
interface, Host port, serial ports, SPI-compatible ports,
UART port, JTAG test and emulation port, timers, flags,
and interrupt controller. These on-chip peripherals can
connect to off-chip devices as shown in Figure 1.
The ADSP-2195 has a 16-bit Host port with DMA capa-
bility that lets external Hosts access on-chip memory. This
24-pin parallel port consists of a 16-pin multiplexed
data/address bus and provides a low-service overhead data
move capability. Configurable for 8- or 16-bits, this port
provides a glueless interface to a wide variety of 8- and 16-bit
microcontrollers. Two chip-selects provide Hosts access to
the DSP’s entire memory map. The DSP is bootable
through this port.
The ADSP-2195 also has an external memory interface that
is shared by the DSP’s core, the DMA controller, and DMA
capable peripherals, which include the UART, SPORT0,
SPORT1, SPORT2, SPI0, SPI1, and the Host port. The
external port consists of a 16-bit data bus, a 22-bit address
bus, and control signals. The data bus is configurable to
provide an 8 or 16 bit interface to external memory. Support
for word packing lets the DSP access 16- or 24-bit words
from external memory regardless of the external data bus
width. When configured for an 8-bit interface, the unused
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Figure 1. ADSP-2195 System Diagram
eight lines provide eight programmable, bidirectional gen-
eral-purpose Programmable Flag lines, six of which can be
mapped to software condition signals.
The memory DMA controller lets the ADSP-2195 move
data and instructions from between memory spaces: inter-
nal-to-external, internal-to-internal, and external-to-
external. On-chip peripherals can also use this controller for
DMA transfers.
The ADSP-2195 can respond to up to seventeen interrupts
at any given time: three internal (stack, emulator kernel, and
power-down), two external (emulator and reset), and twelve
user-defined (peripherals) interrupts. Programmers assign
REV. PrA
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
5
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