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PDF ADSP-2191M Data sheet ( Hoja de datos )
| Número de pieza | ADSP-2191M | |
| Descripción | DSP Microcomputer | |
| Fabricantes | Analog Devices | |
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a
DSP Microcomputer
ADSP-2191M
PERFORMANCE FEATURES
6.25 ns Instruction Cycle Time, for up to 160 MIPS
Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy to Use Algebraic Syntax
Single-Cycle Instruction Execution
Single-Cycle Context Switch between Two Sets of Com-
putation and Memory Instructions
Instruction Cache Allows Dual Operand Fetches in Every
Instruction Cycle
Multifunction Instructions
Pipelined Architecture Supports Efficient Code
Execution
Architectural Enhancements for Compiled C and C++
Code Efficiency
Architectural Enhancements beyond ADSP-218x Family
are Supported with Instruction Set Extensions for
Added Registers, and Peripherals
Flexible Power Management with User-Selectable
Power-Down and Idle Modes
FUNCTIONAL BLOCK DIAGRAM
INTERNAL MEMORY
FOUR INDEPENDENT BLOCKS
ADSP-219x
DSP CORE
CACHE
64 ؋ 24-BIT
ADDRESS
24 BIT
DATA
ADDRESS 24 BIT
DATA
ADDRESS 16 BIT
DATA
ADDRESS
16 BIT
DATA
JTAG
TEST &
EMULATION
6
DAG1
4 ؋ 4 ؋ 16
DAG2
4 ؋ 4 ؋ 16
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
24
DMA
CONNECT
PM DATA BUS
PX
24
DM DATA BUS
16
DATA
REGISTER
FILE
INPUT
REGISTERS
MULT
RESULT
REGISTERS
16 ؋ 16-BIT
BARREL
SHIFTER
ALU
EXTERNAL PORT
I/O ADDRESS 18
24 DMA ADDRESS
24 DMA DATA
16 I/O DATA
ADDR BUS
MUX
DATA BUS
MUX
I/O PROCESSOR
I/O REGISTERS
(MEMORY-MAPPED)
CONTROL
STATUS
BUFFERS
DMA
CONTROLLER
HOST PORT
SERIAL PORTS
(3)
SPI PORTS
(2)
SYSTEM INTERRUPT CONTROLLER
UART PORT
(1)
PROGRAMMABLE
FLAGS (16)
TIMERS (3)
22
16
24
18
6
2
3
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2002
1 page  
ADSP-2191M
INTEGRATION FEATURES
160K Bytes On-Chip RAM Configured as 32K Words 24-Bit
Memory RAM and 32K Words 16-Bit Memory RAM
Dual-Purpose 24-Bit Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-Bit
Accumulators
Unified Memory Space Allows Flexible Address Genera-
tion, Using Two Independent DAG Units
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Enhanced Interrupt Controller Enables Programming of
Interrupt Priorities and Nesting Modes
SYSTEM INTERFACE FEATURES
Host Port with DMA Capability for Glueless 8- or 16-Bit
Host Interface
16-Bit External Memory Interface for up to 16M Words of
Addressable Memory Space
Three Full-Duplex Multichannel Serial Ports, with
Support for H.100 and up to 128 TDM Channels with
A-Law and -Law Companding Optimized for Telecom-
munications Systems
Two SPI-Compatible Ports with DMA Support
UART Port with DMA Support
16 General-Purpose I/O Pins with Integrated Interrupt
Support
Three Programmable Interval Timers with PWM
Generation, PWM Capture/Pulsewidth Measurement,
and External Event Counter Capabilities
Up to 11 DMA Channels Can Be Active at Any Given Time
for High I/O Throughput
On-Chip Boot ROM for Automatic Booting from External
8- or 16-Bit Host Device, SPI ROM, or UART with
Autobaud Detection
Programmable PLL Supports 1؋ to 32؋ Input Frequency
Multiplication and Can Be Altered during Runtime
IEEE JTAG Standard 1149.1 Test Access Port Supports
On-Chip Emulation and System Debugging
2.5 V Internal Operation and 3.3 V I/O
144-Lead LQFP and 144-Ball Mini-BGA Packages
TABLE OF CONTENTS
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . .3
DSP Core Architecture . . . . . . . . . . . . . . . . . . . . . . . .3
DSP Peripherals Architecture . . . . . . . . . . . . . . . . . . .4
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . .5
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Host Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
DSP Serial Ports (SPORTs) . . . . . . . . . . . . . . . . . . . .8
Serial Peripheral Interface (SPI) Ports . . . . . . . . . . . . .9
UART Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Programmable Flag (PFx) Pins . . . . . . . . . . . . . . . . . .9
Low Power Operation . . . . . . . . . . . . . . . . . . . . . . . .10
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Power Supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Booting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Request and Bus Grant . . . . . . . . . . . . . . . . . . .12
Instruction Set Description . . . . . . . . . . . . . . . . . . . .13
Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . .13
Additional Information . . . . . . . . . . . . . . . . . . . . . . .15
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . .15
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . .18
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . .19
ESD SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . .19
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .19
TIMING SPECIFICATIONS . . . . . . . . . . . . . . . . .20
Output Drive Currents . . . . . . . . . . . . . . . . . . . . . . .40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Environmental Conditions . . . . . . . . . . . . . . . . . . . .41
144-Lead LQFP Pinout . . . . . . . . . . . . . . . . . . . . . .43
144-Lead Mini-BGA Pinout . . . . . . . . . . . . . . . . . . .45
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . .47
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . .48
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
–2– REV. A
5 Page 
ADSP-2191M
Host can directly access the DSP’s entire memory space map,
boot memory space, and internal I/O space. To access the DSP’s
internal memory space, a Host steals one cycle per access from
the DSP. A Host access to the DSP’s external memory uses the
external port interface and does not stall (or steal cycles from)
the DSP’s core. Because a Host can access internal I/O memory
space, a Host can control any of the DSP’s I/O mapped
peripherals.
The Host port is most efficient when using the DSP as a slave
and uses DMA to automate the incrementing of addresses for
these accesses. In this case, an address does not have to be trans-
ferred from the Host for every data transfer.
Host Port Acknowledge (HACK) Modes
The Host port supports a number of modes (or protocols) for
generating a HACK output for the host. The host selects ACK
or Ready modes using the HACK_P and HACK pins. The Host
port also supports two modes for address control: Address Latch
Enable (ALE) and Address Cycle Control (ACC) modes. The
DSP auto-detects ALE versus ACC mode from the HALE and
HWR inputs.
The Host port HACK signal polarity is selected (only at reset) as
active high or active low, depending on the value driven on the
HACK_P pin.The HACK polarity is stored into the Host port
configuration register as a read only bit.
The DSP uses HACK to indicate to the Host when to complete
an access. For a read transaction, a Host can proceed and
complete an access when valid data is present in the read buffer
and the Host port is not busy doing a write. For a write transac-
tions, a Host can complete an access when the write buffer is not
full and the Host port is not busy doing a write.
Two mode bits in the Host Port configuration register HPCR
[7:6] define the functionality of the HACK line. HPCR6 is ini-
tialized at reset based on the values driven on HACK and
HACK_P pins (shown in Table 5); HPCR7 is always cleared (0)
at reset. HPCR [7:6] can be modified after reset by a write access
to the Host port configuration register.
Table 5. Host Port Acknowledge Mode Selection
Values Driven At
Reset
HACK_P HACK
00
01
10
11
HPCR [7:6]
Initial Values
Bit 7 Bit 6
01
00
00
01
Acknowledge
Mode
Ready Mode
ACK Mode
ACK Mode
Ready Mode
The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):
• ACK Mode—Acknowledge is active on strobes; HACK
goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The Host port then removes the HACK.
• Ready Mode—Ready active on strobes, goes low to insert
waitstate during the access.If the Host port cannot
complete the access, it deasserts the HACK/READY line.
In this case, the Host has to extend the access by keeping
the strobe asserted. When the Host samples the HACK
asserted, it can then proceed and complete the access by
deasserting the strobe.
While in Address Cycle Control (ACC) mode and the ACK or
Ready acknowledge modes, the HACK is returned active for any
address cycle.
Host Port Chip Selects
There are two chip-select signals associated with the Host port:
HCMS and HCIOMS. The Host Chip Memory Select (HCMS)
lets the Host select the DSP and directly access the DSP’s inter-
nal/external memory space or boot memory space. The Host
Chip I/O Memory Select (HCIOMS) lets the Host select the
DSP and directly access the DSP’s internal I/O memory space.
Before starting a direct access, the Host configures Host port
interface registers, specifying the width of external data bus
(8- or 16-bit) and the target address page (in the IJPG register).
The DSP generates the needed memory select signals during the
access, based on the target address. The Host port interface
combines the data from one, two, or three consecutive Host
accesses (up to one 24-bit value) into a single DMA bus access
to prefetch Host direct reads or to post direct writes. During
assembly of larger words, the Host port interface asserts ACK for
each byte access that does not start a read or complete a write.
Otherwise, the Host port interface asserts ACK when it has
completed the memory access successfully.
DSP Serial Ports (SPORTs)
The ADSP-2191M incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial and
multiprocessor communications. The SPORTs support the
following features:
• Bidirectional operation—each SPORT has independent
transmit and receive pins.
• Double-buffered transmit and receive ports—each port
has a data register for transferring data words to and from
memory and shift registers for shifting data in and out of
the data registers.
• Clocking—each transmit and receive port can either use
an external serial clock (40 MHz) or generate its own, in
frequencies ranging from 19 Hz to 40 MHz.
• Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.
–8– REV. A
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