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ADSP-2188NBST-320 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2188NBST-320
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-2188NBST-320 Datasheet, Funktion
a
DSP Microcomputer
ADSP-218xN Series
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
Up to 256K Bytes of On-Chip RAM, Configured as
Up to 48K Words Program Memory RAM
Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to On-
Chip Memory (Mode Selectable)
4M-Byte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT
Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
MEMORY
DATA ADDRESS
GENERATORS
PROGRAM
PROGRAM
MEMORY
UP TO
DATA
MEMORY
UP TO
DAG1 DAG2
Insert chip
blSoEcQkUdENiaCgErRaPmRDOAGhTReAAr4eMM8.EKMM؋EOM2RO4Y-RBAYITDADDRDER5S6ESKSS؋
PROGRAM MEMORY DATA
DATA MEMORY DATA
16-BIT
PROGRAMMABLE
I/O
AND
FLAGS
ARITHMETIC UNITS
ALU
MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT0 SPORT1
TIMER
FULL MEMORY MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reli-
able. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. No license is granted by implication or otherwise under
any patent or patent rights of Analog Devices.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
http://www.analog.com
Fax:781/326-8703
© Analog Devices, Inc., 2001






ADSP-2188NBST-320 Datasheet, Funktion
ADSP-218xN Series
Memory Interface Pins
ADSP-218xN series members can be used in one of two
modes: Full Memory Mode, which allows BDMA operation
with full external overlay memory and I/O capability, or
Host Mode, which allows IDMA operation with limited
external addressing capabilities.
The operating mode is determined by the state of the Mode
C pin during RESET and cannot be changed while the
processor is running. Table 3 and Table 4 list the active
signals at specific pins of the DSP during either of the two
operating modes (Full Memory or Host). A signal in one
table shares a pin with a signal from the other table, with the
active signal determined by the mode that is set. For the
shared pins and their alternate signals (e.g., A4/IAD3), refer
to the package pinouts in Table 27 on page 40 and Table 28
on page 42.
Table 3. Full Memory Mode Pins (Mode C = 0)
Pin Name
A13 – 0
D23 – 0
# of Pins
14
24
I/O
O
I/O
Function
Address Output Pins for Program, Data, Byte, and I/O Spaces
Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used
as Byte Memory Addresses.)
Table 4. Host Mode Pins (Mode C = 1)
Pin Name # of Pins I/O
Function
IAD15 – 0
A0
D23 – 8
IWR
IRD
IAL
IS
IACK
16
1
16
1
1
1
1
1
I/O IDMA Port Address/Data Bus
O Address Pin for External I/O, Program, Data, or Byte Access1
I/O Data I/O Pins for Program, Data, Byte, and I/O Spaces
I IDMA Write Enable
I IDMA Read Enable
I IDMA Address Latch Pin
I IDMA Select
O IDMA Port Acknowledge Configurable in Mode D; Open Drain
1In Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals.
Terminating Unused Pins
Table 5 shows the recommendations for terminating
unused pins.
Table 5. Unused Pin Terminations
Pin Name1
XTAL
CLKOUT
A13–1 or
IAD12 – 0
A0
D23 – 8
D7 or
IWR
D6 or
IRD
D5 or
IAL
D4 or
IS
I/O
3-State
(Z)2
O
O
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
I/O (Z)
I
Reset
State
O
O
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z
I
Hi-Z3 Caused By
BR, EBR
IS
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
BR, EBR
Unused Configuration
Float
Float4
Float
Float
Float
Float
Float
High (Inactive)
Float
High (Inactive)
Float
Low (Inactive)
Float
High (Inactive)
–6– REV. 0

6 Page









ADSP-2188NBST-320 pdf, datenblatt
ADSP-218xN Series
MEMORY ARCHITECTURE
The ADSP-218xN series provides a variety of memory and
peripheral interface options. The key functional groups are
Program Memory, Data Memory, Byte Memory, and I/O.
Refer to Figure 3 through Figure 8, Table 8 on page 14, and
Table 9 on page 14 for PM and DM memory allocations in
the ADSP-218xN series.
0X3FFF
PROGRAM MEMORY
MODEB = 1
RESERVED
0X2000
0X1FFF
0X0000
EXTERNAL PM
0X3FFF
0X2000
0X1FFF
0X1000
0X0FFF
0X0000
PROGRAM MEMORY
MODEB = 0
PM OVERLAY 1,2
(EXTERNAL PM)
PM OVERLAY 0
(RESERVED)
RESERVED
INTERNAL PM
DATA MEMORY
0X3FFF
0X3FE0
0X3FDF
0X3000
0X2FFF
0X2000
0X1FFF
0X0000
32 MEMORY-MAPPED
CONTROL REGISTERS
4064 RESERVED
WORDS
INTERNAL DM
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY 0
(RESERVED)
Figure 3. ADSP-2184 Memory Architecture
0X3FFF
PROGRAM MEMORY
MODEB = 1
RESERVED
0X2000
0X1FFF
0X0000
EXTERNAL PM
0X3FFF
0X2000
0X1FFF
PROGRAM MEMORY
MODEB = 0
PM OVERLAY 1,2
(EXTERNAL PM)
PM OVERLAY 0
(RESERVED)
INTERNAL PM
0X0000
DATA MEMORY
0X3FFF
0X3FE0
0X3FDF
32 MEMORY-MAPPED
CONTROL REGISTERS
INTERNAL DM
0X2000
0X1FFF
0X0000
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY 0
(INTERNAL DM)
Figure 4. ADSP-2185 Memory Architecture
0X3FFF
PROGRAM MEMORY
MODEB = 1
RESERVED
0X2000
0X1FFF
0X0000
EXTERNAL PM
0X3FFF
0X2000
0X1FFF
PROGRAM MEMORY
MODEB = 0
PM OVERLAY 1,2
(EXTERNAL PM)
PM OVERLAY 0
(RESERVED)
INTERNAL PM
0X0000
DATA MEMORY
0X3FFF
0X3FE0
0X3FDF
32 MEMORY-MAPPED
CONTROL REGISTERS
INTERNAL DM
0X2000
0X1FFF
0X0000
DM OVERLAY 1,2
(EXTERNAL DM)
DM OVERLAY 0
(RESERVED)
Figure 5. ADSP-2186 Memory Architecture
–12–
REV. 0

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