ADSP-2186NBCA-320 Datasheet PDF ( Pinout )

ADSP-2186NBCA-320 Datasheet PDF - Analog Devices

Part Number	*ADSP-2186NBCA-320*
Description	DSP Microcomputer
Manufacturers	Analog Devices
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DSP Microcomputer

ADSP-218xN Series

PERFORMANCE FEATURES

12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS

Sustained Performance

Single-Cycle Instruction Execution

Single-Cycle Context Switch

3-Bus Architecture Allows Dual Operand Fetches in

Every Instruction Cycle

Multifunction Instructions

Power-Down Mode Featuring Low CMOS Standby

Power Dissipation with 200 CLKIN Cycle Recovery

from Power-Down Condition

Low Power Dissipation in Idle Mode

INTEGRATION FEATURES

ADSP-2100 Family Code Compatible (Easy to Use

Algebraic Syntax), with Instruction Set Extensions

Up to 256K Bytes of On-Chip RAM, Configured as

Up to 48K Words Program Memory RAM

Up to 56K Words Data Memory RAM

Dual-Purpose Program Memory for Both Instruction and

Data Storage

Independent ALU, Multiplier/Accumulator, and Barrel

Shifter Computational Units

Two Independent Data Address Generators

Powerful Program Sequencer Provides Zero Overhead

Looping Conditional Instruction Execution

Programmable 16-Bit Interval Timer with Prescaler

100-Lead LQFP and 144-Ball Mini-BGA

SYSTEM INTERFACE FEATURES

Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation

All Inputs Tolerate up to 3.6 V Regardless of Mode

16-Bit Internal DMA Port for High-Speed Access to On-

Chip Memory (Mode Selectable)

4M-Byte Memory Interface for Storage of Data Tables

and Program Overlays (Mode Selectable)

8-Bit DMA to Byte Memory for Transparent Program and

Data Memory Transfers (Mode Selectable)

Programmable Memory Strobe and Separate I/O

Memory Space Permits “Glueless” System Design

Programmable Wait State Generation

Two Double-Buffered Serial Ports with Companding

Hardware and Automatic Data Buffering

Automatic Booting of On-Chip Program Memory from

Byte-Wide External Memory, e.g., EPROM, or through

Internal DMA Port

Six External Interrupts

13 Programmable Flag Pins Provide Flexible System

Signaling

UART Emulation through Software SPORT

Reconfiguration

ICE-Port™ Emulator Interface Supports Debugging in

Final Systems

FUNCTIONAL BLOCK DIAGRAM

POWER-DOWN

CONTROL

MEMORY

DATA ADDRESS

GENERATORS

PROGRAM

MEMORY

UP TO

DATA

MEMORY

UP TO

DAG1 DAG2

Insert chip

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PROGRAM MEMORY DATA

DATA MEMORY DATA

16-BIT

PROGRAMMABLE

I/O

AND

FLAGS

ARITHMETIC UNITS

ALU

MAC SHIFTER

ADSP-2100 BASE

ARCHITECTURE

SERIAL PORTS

SPORT0 SPORT1

TIMER

FULL MEMORY MODE

EXTERNAL

ADDRESS

BUS

EXTERNAL

DATA

BUS

BYTE DMA

CONTROLLER

EXTERNAL

DATA

BUS

INTERNAL

DMA

PORT

HOST MODE

ICE-Port is a trademark of Analog Devices, Inc.

REV. 0

Information furnished by Analog Devices is believed to be accurate and reli-

able. However, no responsibility is assumed by Analog Devices for its use,

nor for any infringements of patents or other rights of third parties that may

result from its use. No license is granted by implication or otherwise under

any patent or patent rights of Analog Devices.

One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:781/329-4700

http://www.analog.com

Fax:781/326-8703

ADSP-218xN Series

Table 2. Common-Mode Pins

Pin Name

# of Pins I/O

Function

RESET

BGH

DMS

PMS

IOMS

BMS

1 I Processor Reset Input

1 I Bus Request Input

1 O Bus Grant Output

1 O Bus Grant Hung Output

1 O Data Memory Select Output

1 O Program Memory Select Output

1 O Memory Select Output

1 O Byte Memory Select Output

CMS

IRQ2

PF7

IRQL1

PF6

IRQL0

PF5

IRQE

PF4

1 O Combined Memory Select Output

1 O Memory Read Enable Output

1 O Memory Write Enable Output

1 I Edge- or Level-Sensitive Interrupt Request1

I/O Programmable I/O pin

1 I Level-Sensitive Interrupt Requests1

I/O Programmable I/O Pin

1 I Level-Sensitive Interrupt Requests1

I/O Programmable I/O Pin

1 I Edge-Sensitive Interrupt Requests1

I/O Programmable I/O Pin

Mode D

PF3

Mode C

PF2

Mode B

PF1

Mode A

PF0

CLKIN

XTAL

CLKOUT

SPORT0

SPORT1

IRQ1–0, FI, FO

PWD

PWDACK

FL0, FL1, FL2

VDDINT

VDDEXT

GND

VDDINT

VDDEXT

GND

EZ-Port

I Mode Select Input—Checked Only During RESET

I/O Programmable I/O Pin During Normal Operation

I Mode Select Input—Checked Only During RESET

I/O Programmable I/O Pin During Normal Operation

I Mode Select Input—Checked Only During RESET

I/O Programmable I/O Pin During Normal Operation

I Mode Select Input—Checked Only During RESET

I/O Programmable I/O Pin During Normal Operation

I Clock Input

O Quartz Crystal Output

O Processor Clock Output

I/O Serial Port I/O Pins

Edge- or Level-Sensitive Interrupts, FI, FO2

I Power-Down Control Input

O Power-Down Acknowledge Control Output

O Output Flags

I Internal VDD (1.8 V) Power (LQFP)

I External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP)

I Ground (LQFP)

I Internal VDD (1.8 V) Power (Mini-BGA)

I External VDD (1.8 V, 2.5 V, or 3.3 V) Power (Mini-

BGA)

I Ground (Mini-BGA)

I/O For Emulation Use

1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will

vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable

flag.

2SPORT configuration determined by the DSP System Control Register. Software configurable.

REV. 0

–5–

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ADSP-2186NBCA-320 Datasheet PDF - Analog Devices

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