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ADSP-2186KST-133 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2186KST-133
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 36 Seiten
ADSP-2186KST-133 Datasheet, Funktion
a
DSP Microcomputer
ADSP-2186
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time 40 MIPS Sustained
Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Memory RAM and
8K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
144-Ball Mini-BGA
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Byte Memory Interface for Storage of Data
Tables and Program Overlays
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
(Mode Selectable)
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
ICE-Port is a trademark of Analog Devices, Inc.
All trademarks are the property of their respective holders.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS PROGRAM
SEQUENCER
DAG 1 DAG 2
POWER-DOWN
CONTROL
MEMORY
8K ؋ 24 8K ؋ 16
PROGRAM DATA
MEMORY MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
TIMER
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
GENERAL DESCRIPTION
The ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2186 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2186 integrates 40K bytes of on-chip memory con-
figured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2186 is available in 100-lead LQFP and
144-Ball Mini-BGA packages.
In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999






ADSP-2186KST-133 Datasheet, Funktion
ADSP-2186
Idle
When the ADSP-2186 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
In Idle mode IDMA, BDMA and autobuffer cycle steals still
occur.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2186 to let the
processor’s internal clock signal be slowed, further reducing
power consumption. The reduced clock frequency, a program-
mable fraction of the normal clock rate, is specified by a select-
able divisor given in the IDLE instruction. The format of the
instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2186 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows typical basic system configurations with the
ADSP-2186, two serial devices, a byte-wide EPROM and optional
external program and data overlay memories (mode selectable).
Programmable wait state generation allows the processor to
connect easily to slow peripheral devices. The ADSP-2186 also
provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0). Additional system peripherals can
be added in this mode through the use of external hardware to
generate and latch address signals.
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
FULL MEMORY MODE
ADSP-2186
CLKIN
XTAL
ADDR13–0
14
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
DATA23–0
BMS
24
MODE C/PF2
MODE B/PF1
MODE A/PF0
IOMS
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
A13–0
D23–16
D15–8
A0–A21
DATA
BYTE
MEMORY
CS
A10–0
D23–8
A13–0
D23–0
ADDR
I/O SPACE
DATA (PERIPHERALS)
CS 2048 LOCATIONS
ADDR OVERLAY
MEMORY
DATA
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
HOST MEMORY MODE
ADSP-2186
1/2x CLOCK
OR
CRYSTAL
CLKIN
XTAL
FL0–2
PF3
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
1
ADDR0
DATA23–8
BMS
16
MODE C/PF2
MODE B/PF1
MODE A/PF0
SERIAL
DEVICE
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
IOMS
SPORT0
SCLK0
PMS
DMS
SERIAL
DEVICE
RFS0
TFS0
DT0
DR0
CMS
BR
BG
BGH
SYSTEM
INTERFACE
OR
CONTROLLER
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
PWD
PWDACK
IAD15–0
16
Figure 2. Basic System Configuration
–6– REV. A

6 Page









ADSP-2186KST-133 pdf, datenblatt
ADSP-2186
I/O Space Instructions
The instructions used to access the ADSP-2186’s I/O memory
space are as follows:
Syntax: IO(addr) = dreg
dreg = IO(addr);
where addr is an address value between 0 and 2047 and dreg is
any of the 16 data registers.
Examples: IO(23) = AR0;
AR1 = IO(17);
Description: The I/O space read and write instructions move
data between the data registers and the I/O
memory space.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2186 has on-chip emulation support and an
ICE-Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
Emulation Reset and the Mode Pins
The Mode A, B, and C pins are located on the rising edge of the
RESET signal. However, when the emulator reset (ERESET) is
asserted by the EZ-ICE, the DSP performs a chip reset, and the
initial mode information is erased, and the logic values on the
mode pins are latched. You must take into consideration the
value of the mode pins before issuing a chip reset command
from the EZ-ICE user interface. If you are using a passive
method of maintaining mode information (as discussed in Set-
ting Memory Modes) then it does not matter that the mode
information is latched by an emulator reset. However, if you are
using the RESET pin as a method of setting the value of the
mode pins, then you have to take into consideration the effects
of an emulator reset.
One method of ensuring that the values located on the mode
pins is the one that is desired to construct a circuit like the one
shown in Figure 9. This circuit will force the value located on
the Mode C pin to zero; regardless if it latched via the RESET
or ERESET pin.
ERESET
RESET
ADSP-2186
1k
MODE A/PFO
PROGRAMMABLE I/O
Figure 9. Boot Mode Circuit
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
The ICE-Port interface consists of the following ADSP-2186
pins:
EBR
EMS
ELIN
EBG
EINT
ELOUT
ERESET
ECLK
EE
These ADSP-2186 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or
pull-down resistors. The traces for these signals between the
ADSP-2186 and the connector must be kept as short as pos-
sible, no longer than three inches.
The following pins are also used by the EZ-ICE:
BR
RESET
BG
GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2186 in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of
the RESET, BR and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The female plug is plugged onto the
14-pin connector (a pin strip header) on the target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 10. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
1
GND
3
EBG
EBR
5
7
KEY (NO PIN)
ELOUT
EE
RESET
9
11
13
2
BG
4
BR
6
EINT
8
ELIN
10
ECLK
12
EMS
14
ERESET
TOP VIEW
Figure 10. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.
–12–
REV. A

12 Page





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