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ADSP-2185LKST-115 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2185LKST-115
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 31 Seiten
ADSP-2185LKST-115 Datasheet, Funktion
a
DSP Microcomputer
ADSP-2185L
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 Volts, 52 MIPS
Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as 16K Words
Program Memory RAM and 16K Words
Data Memory RAM
Dual Purpose Program Memory for Instruction␣ and Data
Storage
Independent ALU, Multiplier/Accumulator and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory (Mode Selectable)
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program
and Data Memory Transfers (Mode Selectable)
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
UART Emulation through Software SPORT Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
16K؋24 PM
16K؋16 DM
( ) ( )8K؋24 OVERLAY 1
8K؋24 OVERLAY 2
8K؋16 OVERLAY 1
8K؋16 OVERLAY 2
PROGRAMMABLE
I/O
AND
FLAGS
FULL MEMORY
MODE
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
EXTERNAL
DATA
BUS
BYTE DMA
CONTROLLER
OR
EXTERNAL
DATA
BUS
INTERNAL
DMA
PORT
HOST MODE
GENERAL NOTE
This data sheet represents specifications for the ADSP-2185L
3.3 V processor.
GENERAL DESCRIPTION
The ADSP-2185L is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2185L combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
The ADSP-2185L integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM, and 16K
words (16-bit) of data RAM. Power-down circuitry is also pro-
vided to meet the low power needs of battery operated portable
equipment. The ADSP-2185L is available in 100-lead LQFP
package.
In addition, the ADSP-2185L supports instructions which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
ALU constants, multiplication instruction (x squared), biased
rounding, result free ALU operations, I/O memory transfers and
global interrupt masking, for increased flexibility.
Fabricated in a high speed, low power, CMOS process, the
ADSP-2185L operates with a 19 ns instruction cycle time. Ev-
ery instruction can execute in a single processor cycle.
␣␣
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998






ADSP-2185LKST-115 Datasheet, Funktion
ADSP-2185L
LOW POWER OPERATION
The ADSP-2185L has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2185L processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
• Quick recovery from power-down. The processor begins ex-
ecuting instructions in as few as 400 CLKIN cycles.
• Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the 400 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 400 CLKIN cycle start up.
• Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit Interrupt support allows
an unlimited number of instructions to be executed before op-
tionally powering down. The power-down interrupt also can
be used as a non-maskable, edge-sensitive interrupt.
• Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
• The RESET pin also can be used to terminate power-down.
• Power-down acknowledge pin indicates when the processor
has entered power-down.
Idle
When the ADSP-2185L is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then con-
tinues with the instruction following the IDLE instruction. In
Idle Mode IDMA, BDMA and autobuffer cycle steals still occur.
Slow Idle
The IDLE instruction on the ADSP-2185L slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the nor-
mal clock rate, is specified by a selectable divisor given in the
IDLE instruction. The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. The one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2185L will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2185L, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode se-
lectable). Programmable wait state generation allows the proces-
sor to connect easily to slow peripheral devices. The ADSP-2185L
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode al-
lows access to the full external data bus, but limits addressing to
a single address bit (A0). Additional system peripherals can be
added in this mode through the use of external hardware to gen-
erate and latch address signals.
Clock Signals
The ADSP-2185L can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed in-
formation on this power-down feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
The ADSP-2185L uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally, in-
structions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2185L includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
–6– REV. A

6 Page









ADSP-2185LKST-115 pdf, datenblatt
ADSP-2185L
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The ADSP-2185L has on-chip emulation support and an ICE-
Port, a special set of pins that interface to the EZ-ICE. These
features allow in-circuit emulation without replacing the target
system processor by using only a 14-pin connection from the
target system to the EZ-ICE. Target systems must have a 14-pin
connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete in-
formation on ICE products.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining
mode information (as discussed in Setting Memory Modes)
then it does not matter that the mode information is latched by
an emulator reset. However, if you are using the RESET pin as
a method of setting the value of the mode pins, then you have to
take into consideration the effects of an emulator reset.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 9. This circuit forces the value located on the Mode A
pin to logic high; regardless if it latched via the RESET or
ERESET pin.
ERESET
RESET
ADSP-2185L
1k
MODE A/PFO
PROGRAMMABLE I/O
Figure 9. Mode A Pin/EZ-ICE Circuit
The ICE-Port interface consists of the following ADSP-2185L
pins:
EBR
EMS
ELIN
EBG
EINT
ELOUT
ERESET
ECLK
EE
These ADSP-2185L pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function ex-
cept during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the ADSP-2185L
and the connector must be kept as short as possible, no longer
than three inches.
The following pins are also used by the EZ-ICE:
BR BG
RESET GND
The EZ-ICE uses the EE (emulator enable) signal to take con-
trol of the ADSP-2185L in the target system. This causes the
processor to use its ERESET, EBR and EBG pins instead of the
RESET, BR and BG pins. The BG output is three-stated. These
signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in
length with one end fixed to the EZ-ICE. The female plug is
plugged onto the 14-pin connector (a pin strip header) on the
target board.
Target Board Connector for EZ-ICE Probe
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 10. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow enough
room in your system to fit the EZ-ICE probe onto the 14-pin
connector.
GND
EBG
EBR
KEY (NO PIN)
ELOUT
EE
RESET
1
3
5
7
؋
9
11
13
2
BG
4
BR
6
EINT
8
ELIN
10
ECLK
12
EMS
14
ERESET
TOP VIEW
Figure 10. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug.
Pin strip headers are available from vendors such as 3M,
McKenzie and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
–12–
REV. A

12 Page





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