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ADSP-2183BST-133 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2183BST-133
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 31 Seiten
ADSP-2183BST-133 Datasheet, Funktion
a
DSP Microcomputer
FEATURES
PERFORMANCE
19 ns Instruction Cycle Time from 26.32 MHz Crystal
@ 3.3 Volts
52 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 300 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead LQFP, 144-Ball Mini-BGA
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
ADSP-2183
FUNCTIONAL BLOCK DIAGRAM
POWERDOWN
CONTROL
PROGRAMMABLE
I/O
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
MEMORY
PROGRAM DATA
MEMORY MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
FLAGS
BYTE DMA
CONTROLLER
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
EXTERNAL
DATA
BUS
DMA
BUS
GENERAL DESCRIPTION
The ADSP-2183 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2183 combines the ADSP-2100 family base architec-
ture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and
data memory.
The ADSP-2183 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equipment.
The ADSP-2183 is available in 128-lead LQFP, and 144-Ball
Mini-BGA packages.
In addition, the ADSP-2183 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2183 operates with a 19 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2183’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2183 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADSP-2183BST-133 Datasheet, Funktion
ADSP-2183
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock, and thus its response time, to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the ADSP-2183 will remain in the
idle state for up to a maximum of n processor cycles (n = 16, 32,
64 or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems with an exter-
nally generated serial clock (SCLK), the serial clock rate may be
faster than the processor’s reduced internal clock rate. Under
these conditions, interrupts must not be generated at a faster
rate than can be serviced, due to the additional time the processor
takes to come out of the idle state (a maximum of n processor
cycles).
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2183, two serial devices, a byte-wide EPROM and
optional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. The ADSP-2183 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
The ADSP-2183 uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
Because the ADSP-2183 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLKODIS bit in the SPORT0 Autobuffer Control
Register.
1/2x CLOCK
OR
CRYSTAL
SERIAL
DEVICE
SERIAL
DEVICE
SYSTEM
INTERFACE
OR
CONTROLLER
16
ADSP-2183
CLKIN
XTAL
14
ADDR13-0
FL0-2
PF0-7
IRQ2
IRQE
IRQL0
IRQL1
DATA23-0
BMS
24
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
RD
WR
IOMS
SPORT0
SCLK0
RFS0
TFS0
DT0
DR0
IDMA PORT
IRD
IWR
IS
IAL
IACK
IAD15-0
PMS
DMS
CMS
BR
BG
BGH
PWD
PWDACK
A13-0
D23-16
D15-8
A10-0
D23-8
A13-0
D23-0
A0-A21
DATA
CS
BYTE
MEMORY
ADDR
DATA
I/O
SPACE
(PERIPHERALS)
CS
2048 LOCATIONS
ADDR OVERLAY
DATA MEMORY
TWO 8K
PM SEGMENTS
TWO 8K
DM SEGMENTS
Figure 2. ADSP-2183 Basic System Configuration
Clock Signals
The ADSP-2183 can be clocked by either a crystal or a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
CLKIN
XTAL
DSP
CLKOUT
Figure 3. External Crystal Connections
Reset
The RESET signal initiates a master reset of the ADSP-2183.
The RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
mum pulsewidth specification, tRSP.
The RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MSTAT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. The first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
–6– REV. C

6 Page









ADSP-2183BST-133 pdf, datenblatt
ADSP-2183–SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
Parameter
VDD
TAMB
Supply Voltage
Ambient Operating Temperature
ELECTRICAL CHARACTERISTICS
K Grade
Min Max
3.0 3.6
0 +70
B Grade
Min Max
3.0 3.6
–40 +85
Unit
V
°C
Parameter
Test Conditions
K/B Grades
Min Typ Max
Unit
VIH
VIL
VOH
VOL
IIH
IIL
IOZH
IOZL
IDD
IDD
CI
CO
Hi-Level Input Voltage1, 2
Lo-Level Input Voltage1, 3
Hi-Level Output Voltage1, 4, 5
Lo-Level Output Voltage1, 4, 5
Hi-Level Input Current3
Lo-Level Input Current3
Three-State Leakage Current7
Three-State Leakage Current7
Supply Current (Idle)9, 10
Supply Current (Dynamic)10, 12
Input Pin Capacitance3, 6, 13
Output Pin Capacitance6, 7, 13, 14
@ VDD = max
@ VDD = min
@ VDD = min
IOH = –0.5 mA
@ VDD = min
IOH = –100 µA6
@ VDD = min
IOL = 2 mA
@ VDD = max
VIN = VDD max
@ VDD = max
VIN = 0 V
@ VDD = max
VIN = VDD max8
@ VDD = max
VIN = 0 V8
@ VDD = 3.3
TAMB = +25°C
tCK = 19 ns11
tCK = 25 ns11
tCK = 30 ns11
tCK = 34.7 ns11
@ VDD = 3.3
TAMB = +25°C
tCK = 19 ns11
tCK = 25 ns11
tCK = 30 ns11
tCK = 34.7 ns11
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C
@ VIN = 2.5 V
fIN = 1.0 MHz
TAMB = +25°C
2.0
2.4
VDD – 0.3
10
9
8
6
44
35
30
26
0.4
0.4
10
10
10
8
8
8
V
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
mA
mA
mA
mA
mA
pF
pF
NOTES
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, IAD0–IAD15, PF0–PF7.
12Input only pins: RESET, IRQ2, BR, MMAP, DR0, DR1, PWD, IRQL0, IRQL1, IRQE, IS, IRD, IWR, IAL.
13Input only pins: CLKIN, RESET, IRQ2, BR, MMAP, DR0, DR1, IS, IAL, IRD, IWR, IRQL0, IRQL1, IRQE, PWD.
14Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, IACK, PWDACK, A0–A13, DT0, DT1, CLKOUT, FL2-0.
15Although specified for TTL outputs, all ADSP-2183 outputs are CMOS-compatible and will drive to V DD and GND, assuming no dc loads.
16Guaranteed but not tested.
17Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–IAD15, PF0–PF7.
180 V on BR, CLKIN Active (to force three-state condition).
19Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10Current reflects device operating with no output loads.
11VIN = 0.4 V and 2.4 V. For typical figures for supply currents, refer to Power Dissipation section.
12IDD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (types 1, 4, 5, 12, 13, 14), 30% are
1type 2 and type 6, and 20% are idle instructions.
13Applies to LQFP package type and Mini-BGA.
14Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–12–
REV. C

12 Page





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