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PDF ADSP-2181KST-160 Data sheet ( Hoja de datos )
| Número de pieza | ADSP-2181KST-160 | |
| Descripción | DSP Microcomputer | |
| Fabricantes | Analog Devices | |
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a
DSP Microcomputer
ADSP-2181
FEATURES
PERFORMANCE
25 ns Instruction Cycle Time from 20 MHz Crystal
@ 5.0 Volts
40 MIPS Sustained Performance
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from
Power-Down Condition
Low Power Dissipation in Idle Mode
INTEGRATION
ADSP-2100 Family Code Compatible, with Instruction
Set Extensions
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Memory RAM
16K Words On-Chip Data Memory RAM
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Programmable 16-Bit Interval Timer with Prescaler
128-Lead TQFP/128-Lead PQFP
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Memory
4 MByte Memory Interface for Storage of Data Tables
and Program Overlays
8-Bit DMA to Byte Memory for Transparent
Program and Data Memory Transfers
I/O Memory Interface with 2048 Locations Supports
Parallel Peripherals
Programmable Memory Strobe and Separate I/O Memory
Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Internal DMA Port
Six External Interrupts
13 Programmable Flag Pins Provide Flexible System
Signaling
ICE-Port™ Emulator Interface Supports Debugging
in Final Systems
ICE-Port is a trademark of Analog Devices, Inc.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
POWER-DOWN
CONTROL
MEMORY
PROGRAM DATA
MEMORY MEMORY
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
PROGRAM MEMORY DATA
DATA MEMORY DATA
PROGRAMMABLE
I/O
FLAGS
BYTE DMA
CONTROLLER
EXTERNAL
ADDRESS
BUS
EXTERNAL
DATA BUS
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
DMA BUS
GENERAL DESCRIPTION
The ADSP-2181 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
The ADSP-2181 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities, and on-chip program and data
memory.
The ADSP-2181 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM, and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. The ADSP-2181 is available in 128-lead TQFP and 128-
lead PQFP packages.
In addition, the ADSP-2181 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking for increased flexibility.
Fabricated in a high speed, double metal, low power, CMOS
process, the ADSP-2181 operates with a 25 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-2181’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2181 can:
• Generate the next program address
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
ADSP-2181
Table I. Interrupt Priority and Interrupt Vector Addresses
Source of Interrupt
Interrupt Vector
Address (Hex)
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
IRQL1
IRQL0
002C
0004
0008
000C
SPORT0 Transmit
0010
SPORT0 Receive
IRQE
0014
0018
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
001C
0020
0024
Timer
0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
The ADSP-2181 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
The IFC register is a write-only register used to force and clear
interrupts.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
The following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LOW POWER OPERATION
The ADSP-2181 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
• Power-Down
• Idle
• Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The ADSP-2181 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. For detailed information about the power-
down feature, refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter.
• Quick recovery from power-down. The processor begins
executing instructions in as few as 100 CLKIN cycles.
• Support for an externally generated TTL or CMOS
processor clock. The external clock can continue running
during power-down without affecting the lowest power
rating and 100 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 100 CLKIN
cycle start up.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit.
• Interrupt support allows an unlimited number of instruc-
tions to be executed before optionally powering down.
The power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.
• Context clear/save control allows the processor to con-
tinue where it left off or start with a clean context when
leaving the power-down state.
• The RESET pin also can be used to terminate power-
down.
• Power-down acknowledge pin indicates when the proces-
sor has entered power-down.
Idle
When the ADSP-2181 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.
Slow Idle
The IDLE instruction is enhanced on the ADSP-2181 to let
the processor’s internal clock signal be slowed, further
reducing power consumption. The reduced clock fre-
quency, a programmable fraction of the normal clock rate,
is specified by a selectable divisor given in the IDLE in-
struction. The format of the instruction is
IDLE (n);
where n = 16, 32, 64 or 128. This instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. The default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.
REV. D
–5–
5 Page 
ADSP-2181
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 x 0.1 inches. The pin strip header must have
at least 0.15 inch clearance on all sides to accept the EZ-ICE
probe plug. Pin strip headers are available from vendors such as
3M, McKenzie and Samtec.
Target Memory Interface
For your target system to be compatible with the EZ-ICE emu-
lator, it must comply with the memory interface guidelines listed
below.
PM, DM, BM, IOM and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM) and Composite
Memory (CM) external interfaces to comply with worst case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst case specification for
some memory access timing requirements and switching
characteristics.
Note: If your target does not meet the worst case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency. De-
pending on the severity of the specification violation, you may
have trouble manufacturing your system as DSP components
statistically vary in switching characteristic and timing require-
ments within published limits.
Restriction: All memory strobe signals on the ADSP-2181
(RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your
target system must have 10 kΩ pull-up resistors connected when
the EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
Target System Interface Signals
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
• EZ-ICE emulation introduces an 8 ns propagation delay be-
tween your target circuitry and the DSP on the RESET
signal.
• EZ-ICE emulation introduces an 8 ns propagation delay be-
tween your target circuitry and the DSP on the BR signal.
• EZ-ICE emulation ignores RESET and BR when single-
stepping.
• EZ-ICE emulation ignores RESET and BR when in Emulator
Space (DSP halted).
• EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
Target Architecture File
The EZ-ICE software lets you load your program in its linked
(executable) form. The EZ-ICE PC program can not load sec-
tions of your executable located in boot pages (by the linker).
With the exception of boot page 0 (loaded into PM RAM), all
sections of your executable mapped into boot pages are not
loaded.
Write your target architecture file to indicate that only PM
RAM is available for program storage, when using the EZ-ICE
software’s loading feature. Data can be loaded to PM RAM or
DM RAM.
REV. D
–11–
11 Page | ||
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