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ADSP-2171 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-2171
Beschreibung DSP Microcomputer
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-2171 Datasheet, Funktion
a
DSP Microcomputer
ADSP-2171/ADSP-2172/ADSP-2173
FEATURES
30 ns Instruction Cycle Time (33 MIPS) from
16.67 MHz Crystal at 5.0 V
50 ns Instruction Cycle Time (20 MIPS) from 10 MHz
Crystal at 3.3 V
ADSP-2100 Family Code & Function Compatible with
New Instruction Set Enhancements for Bit Manipula-
tion Instructions, Multiplication Instructions, Biased
Rounding, and Global Interrupt Masking
Bus Grant Hang Logic
2K Words of On-Chip Program Memory RAM
2K Words of On-Chip Data Memory RAM
8K Words of On-Chip Program Memory ROM
(ADSP-2172)
8- or 16-Bit Parallel Host Interface Port
300 mW Typical Power Dissipation at 5.0 V at 30 ns
70 mW Typical Power Dissipation at 3.3 V at 50 ns
Powerdown Mode Featuring Less than 0.55 mW (ADSP-
2171/ADSP-2172) or 0.36 mW (ADSP-2173) CMOS
Standby Power Dissipation with 100 Cycle Recovery
from Powerdown
Dual Purpose Program Memory for Both Instruction
and Data Storage
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
Two Independent Data Address Generators
Powerful Program Sequencer Provides
Zero Overhead Looping
Conditional Instruction Execution
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Programmable 16-Bit Interval Timer with Prescaler
Programmable Wait State Generation
Automatic Booting of Internal Program Memory from
Byte-Wide External Memory, e.g., EPROM, or
Through Host Interface Port
Stand-Alone ROM Execution (Optional)
Single-Cycle Instruction Execution
Single-Cycle Context Switch
Multifunction Instructions
Three Edge- or Level-Sensitive External Interrupts
Low Power Dissipation in Standby Mode
128-Lead TQFP and 128-Lead PQFP
GENERAL DESCRIPTION
The ADSP-2171, ADSP-2172, and ADSP-2173 are single-chip
microcomputers optimized for digital signal processing (DSP)
and other high-speed numeric processing applications. The
ADSP-2171 and ADSP-2172 are designed for 5.0 V applica-
tions. The ADSP-2173 is designed for 3.3 V applications. The
ADSP-2172 also has 8K words (24-bit) of program ROM.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
DATA
ADDRESS
GENERATORS
DAG 1 DAG 2
PROGRAM
SEQUENCER
PROGRAM
ROM
8K x 24
PROGRAM
RAM
2K x 24
MEMORY
DATA
MEMORY
2K x 16
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
POWERDOWN
CONTROL
LOGIC
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
ARITHMETIC UNITS
ALU MAC SHIFTER
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
EXTERNAL
DATA
BUS
HOST
INTERFACE
PORT
The ADSP-217x combines the ADSP-2100 base architecture
(three computational units, data address generators, and a pro-
gram sequencer) with two serial ports, a host interface port, a
programmable timer, extensive interrupt capabilities, and on-
chip program and data memory.
In addition, the ADSP-217x supports new instructions, which
include bit manipulations–bit set, bit clear, bit toggle, bit test–
new ALU constants, new multiplication instruction (x squared),
biased rounding, and global interrupt masking, for increased
flexibility. The ADSP-217x also has a Bus Grant Hang Logic
(BGH) feature.
The ADSP-217x provides 2K words (24-bit) of program RAM
and 2K words (16-bit) of data memory. The ADSP-2172 pro-
vides an additional 8K words (24-bit) of program ROM. Power-
down circuitry is also provided to meet the low power needs of
battery operated portable equipment. The ADSP-217x is avail-
able in 128-pin TQFP and 128-pin PQFP packages.
Fabricated in a high-speed, double metal, low power, CMOS
process, the ADSP-217X operates with a 30 ns instruction cycle
time. Every instruction can execute in a single processor cycle.
The ADSP-217x’s flexible architecture and comprehensive in-
struction set allow the processor to perform multiple operations
in parallel. In one processor cycle the ADSP-217x can:
generate the next program address
fetch the next instruction
perform one or two data moves
update one or two data address pointers
perform a computational operation
This takes place while the processor continues to:
receive and transmit data through the two serial ports
receive and/or transmit data through the host interface port
decrement timer
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703






ADSP-2171 Datasheet, Funktion
ADSP-2171/ADSP-2172/ADSP-2173
LOW POWER OPERATION
The ADSP-217x has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
Powerdown
Idle
Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation. The CLKOUT pin is controlled by Bit 14 of
SPORT0 Autobuffer Control Register, DM[0x3FF3].
Powerdown
The ADSP-217x processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Here is a brief list of powerdown fea-
tures. Refer to the ADSP-2100 Family User’s Manual, Chapter 9
“System Interface” for detailed information about the
powerdown feature.
Powerdown mode holds the processor in CMOS standby with
a maximum current of less than 100 µA in some modes.
Quick recovery from powerdown. The processor begins ex-
ecuting instructions in as few as 100 CLKIN cycles.
Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during
powerdown without affecting the lowest power rating and 100
CLKIN cycle recovery.
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and let-
ting the oscillator run to allow 100 CLKIN cycle startup.
Powerdown is initiated by either the powerdown pin (PWD)
or the software powerdown force bit.
Interrupt support allows an unlimited number of instructions
to be executed before optionally powering down. The
powerdown interrupt also can be used as a non-maskable,
edge sensitive interrupt.
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
powerdown state.
The RESET pin also can be used to terminate powerdown,
and the host software reset feature can be used to terminate
powerdown under certain conditions.
Powerdown acknowledge pin indicates when the processor has
entered powerdown.
Idle
When the ADSP-217x is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then
continues with the instruction following the IDLE instruction.
Slow Idle
The IDLE instruction is enhanced on the ADSP-217x to let the
processor’s internal clock signal be slowed during IDLE, further
reducing power consumption. The reduced clock frequency, a
programmable fraction of the normal clock rate, is specified by a
selectable divisor given in the IDLE instruction. The format of
the instruction is
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts––the 1-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-217x will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64,
or 128) before resuming normal operation.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
SYSTEM INTERFACE
Figure 3 shows a basic system configuration with the ADSP-
217x, two serial devices, a host processor, a boot EPROM, and
optional external program and data memories. Up to 14K words
of data memory and 16K words of program memory can be sup-
ported. Programmable wait state generation allows the processor
to interface easily to slow memories. The ADSP-217x also pro-
vides one external interrupt and two serial ports or three exter-
nal interrupts and one serial port.
Clock Signals
The ADSP-217x can be clocked by either a crystal or by a TTL-
compatible clock signal.
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal opera-
tion. The only exception is while the processor is in the Power-
down State. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual for detailed information on
this powerdown feature.
If an external clock is used, it should be a TTL-compatible sig-
nal running at half the instruction rate. The signal is connected
to the processor’s CLKIN input. When an external clock is
used, the XTAL input must be left unconnected.
The ADSP-217x uses an input clock with a frequency equal to
half the instruction rate; a 16.67 MHz input clock yields a 30 ns
processor cycle (which is equivalent to 33 MHz). Normally, in-
structions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
–6– REV. A

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ADSP-2171 pdf, datenblatt
ADSP-2171/ADSP-2172/ADSP-2173
ROM Enable/Data Memory Wait State
Control Register
0x3FFE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0111111111111111
DWAIT4 DWAIT3 DWAIT2 DWAIT1 DWAIT0
ROM enable
1 = enable
0 = disable
SPORT0 Multichannel Receive Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
0x3FFA
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SPORT0 Multichannel Transmit Word Enable Registers
1 = Channel Enabled
0 = Channel Ignored
0x3FF8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x3FF9
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0x3FF7
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPORT0 Control Register
0x3FF6
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Multichannel Enable MCE
Internal Serial Clock Generation ISCLK
Receive Frame Sync Required RFSR
Receive Frame Sync Width RFSW
Multichannel Frame Delay MFD
Only If Multichannel Mode Enabled
Transmit Frame Sync Required TFSR
Transmit Frame Sync Width TFSW
ITFS Internal Transmit Frame Sync Enable
(or MCL Multichannel Length; 1 = 32 words, 0 = 24 words
Only If Multichannel Mode Enabled)
SLEN Serial Word Length
DTYPE Data Format
00 = right justify, zero-fill unused MSBs
01 = right justify, sign extend into unused MSBs
10 = compand using µ-law
11 = compand using A-law
INVRFS Invert Receive Frame Sync
INVTFS Invert Transmit Frame Sync
(or INVTDV Invert Transmit Data Valid
Only If Multichannel Mode Enabled)
IRFS Internal Receive Frame Sync Enable
Control Registers
–12–
REV. A

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