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ADSP-21062LAB-160 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-21062LAB-160
Beschreibung ADSP-2106x SHARC DSP Microcomputer Family
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 48 Seiten
ADSP-21062LAB-160 Datasheet, Funktion
a
ADSP-2106x SHARC®
DSP Microcomputer Family
ADSP-21062/ADSP-21062L
SUMMARY
High Performance Signal Processor for Communica-
tions, Graphics and Imaging Applications
Super Harvard Architecture
Four Independent Buses for Dual Data Fetch,
Instruction Fetch and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead Thermally Enhanced MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
2 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
CORE PROCESSOR
TIMER INSTRUCTION
CACHE
32 x 48-BIT
DAG1 DAG2
8 x 4 x 32 8 x 4 x 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS 32
BUS
CONNECT
(PX)
PM DATA BUS 48
DM DATA BUS 40/32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
IOD IOA
48 17
JTAG
TEST &
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS &
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. ADSP-21062/ADSP-21062L Block Diagram
4
6
6
36
SHARC is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADSP-21062LAB-160 Datasheet, Funktion
ADSP-21062/ADSP-21062L
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
3
011
ADSP-2106x #3
CLKIN
ADDR31-0
RESET
DATA47-0
RPBA
I D 2-0
CONTROL
CPA
BR1-2, BR4-6
BR3
5
3
010
ADSP-2106x #2
CLKIN
RESET
ADDR31-0
DATA47-0
RPBA
I D 2-0
CONTROL
1x
CLOCK
RESET
CPA
BR1, BR3-6
BR2
5
3
001
ADSP-2106x #1
CLKIN
RESET
ADDR31-0
DATA47-0
RPBA
I D 2-0
RD
WR
ACK
MS3-0
CONTROL
BMS
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
CPA
BR2-6
BR1
5
ADDR
DATA
GLOBAL
MEMORY
OE
WE
ACK
AND
PERIPHERALS
(OPTIONAL)
CS
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
ADDR
DATA
Figure 3. Shared Memory Multiprocessing System
–6– REV. C

6 Page









ADSP-21062LAB-160 pdf, datenblatt
ADSP-21062/ADSP-21062L
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
Connecting CLKIN to Pin 4 of the EZ-ICE header is optional.
The emulator only uses CLKIN when directed to perform
operations such as starting, stopping, and single-stepping mul-
tiple ADSP-2106xs in a synchronous manner. If you do not need
these operations to occur synchronously on the multiple proces-
sors, simply tie Pin 4 of the EZ-ICE header to ground.
If synchronous multiprocessor operations are needed and
CLKIN is connected, clock skew between the multiple ADSP-
21062 processors and the CLKIN pin on the EZ-ICE header
must be minimal. If the skew is too large, synchronous operations
may be off by one or more cycles between processors. For syn-
chronous multiprocessor operation TCK, TMS, CLKIN and
EMU should be treated as critical signals in terms of skew,
and should be laid out as short as possible on your board. If
TCK, TMS, and CLKIN are driving a large number of ADSP-
21062s (more than eight) in your system, then treat them as a
“clock tree” using multiple drivers to minimize skew. (See
Figure 7 “JTAG Clock Tree” and “Clock Distribution” in the
“High Frequency Design Considerations” section of the ADSP-
2106x User’s Manual, Second Edition.)
If synchronous multiprocessor operations are not needed (i.e.,
CLKIN is not connected), just use appropriate parallel termi-
nation on TCK and TMS. TDI, TDO, EMU and TRST are
not critical signals in terms of skew.
For complete information on the SHARC EZ-ICE, see the
ADSP-21000 Family JTAG EZ-ICE User's Guide and Reference.
TDI TDO TDI TDO
TDI TDO
5k
*
TDI
EMU
TCK
TMS
TRST
TDO
CLKIN
TDI TDO TDI TDO
TDI TDO
5k
*
*OPEN DRAIN DRIVER OR EQUIVALENT, i.e.,
EMU
Figure 7. JTAG Clocktree for Multiple ADSP-2106x Systems
SYSTEM
CLKIN
–12–
REV. C

12 Page





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