ADSP-21061LKB-160 Datasheet PDF - Analog Devices
| Part Number | ADSP-21061LKB-160 | |
| Description | ADSP-2106x SHARC DSP Microcomputer Family | |
| Manufacturers | Analog Devices | |
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ADSP-2106x SHARC®
DSP Microcomputer Family
ADSP-21061/ADSP-21061L
SUMMARY
High Performance Signal Computer for Speech, Sound,
Graphics and Imaging Applications
Super Harvard Architecture Computer (SHARC)—
Four Independent Buses for Dual Data, Instructions,
and I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU and Shifter
1 Megabit On-Chip SRAM Memory and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
50 MIPS, 20 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
Pin-Compatible with ADSP-21060 (4 Mbit) and
ADSP-21062 (2 Mbit)
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)
1 Megabit Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable as 32K Words Data Memory (32-Bit), 16K
Words Program Memory (48-Bit) or Combinations of
Both Up to 1 Mbit
Off-Chip Memory Interfacing
4-Gigawords Addressable (32-Bit Address)
Programmable Wait State Generation, Page-Mode DRAM
Support
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
DAG1 DAG2
8 x 4 x 32 8 x 4 x 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
IOD IOA
48 17
JTAG
TEST &
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS 40/32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS &
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
I/O PROCESSOR
Figure 1. ADSP-21061/ADSP-21061L Block Diagram
4
6
6
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
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ADSP-21061/ADSP-21061L
Off-Chip Memory and Peripherals Interface
The ADSP-21061’s external port provides the processor’s inter-
face to off-chip memory and peripherals. The 4-gigaword off-
chip address space is included in the ADSP-21061’s unified
address space. The separate on-chip buses—for program
memory, data memory and I/O—are multiplexed at the external
port to create an external system bus with a single 32-bit address
bus and a single 48-bit (or 32-bit) data bus. The on-chip
Super Harvard Architecture provides three-bus performance,
while the off-chip unified address space gives flexibility to the
designer.
Addressing of external memory devices is facilitated by on-chip
decoding of high order address lines to generate memory bank
select signals. Separate control lines are also generated for sim-
plified addressing of page-mode DRAM. The ADSP-21061
provides programmable memory wait states and external memory
acknowledge controls to allow interfacing to DRAM and peripher-
als with variable access, hold and disable time requirements.
Host Processor Interface
The ADSP-21061’s host interface allows easy connection to
standard microprocessor buses, both 16-bit and 32-bit, with
little additional hardware required. Asynchronous transfers at
speeds up to the full clock rate of the processor are supported.
The host interface is accessed through the ADSP-21061’s exter-
nal port and is memory-mapped into the unified address space.
Two channels of DMA are available for the host interface; code
and data transfers are accomplished with low software overhead.
The host processor requests the ADSP-21061’s external bus
with the host bus request (HBR), host bus grant (HBG) and
ready (REDY) signals. The host can directly read and write the
internal memory of the ADSP-21061, and can access the
DMA channel setup and mailbox registers. Vector interrupt
support is provided for efficient execution of host commands.
DMA Controller
The ADSP-21061’s on-chip DMA controller allows zero-
overhead, nonintrusive data transfers without processor inter-
vention. The DMA controller operates independently and
invisibly to the processor core, allowing DMA operations to
occur while the core is simultaneously executing its program
instructions.
DMA transfers can occur between the ADSP-21061’s internal
memory and either external memory, external peripherals, or a
host processor. DMA transfers can also occur between the
ADSP-21061’s internal memory and its serial ports. DMA
transfers between external memory and external peripheral
devices are another option. External bus packing to 16-, 32-
or 48-bit words is performed during DMA transfers.
Six channels of DMA are available on the ADSP-21061—four
via the serial ports, and two via the processor’s external port (for
either host processor, other ADSP-21061s, memory or I/O
transfers). Programs can be downloaded to the ADSP-21061
using DMA transfers. Asynchronous off-chip peripherals can
control two DMA channels using DMA Request/Grant lines
(DMAR1-2, DMAG1-2). Other DMA features include interrupt
generation upon completion of DMA transfers and DMA chain-
ing for automatic linked DMA transfers.
Serial Ports
The ADSP-21061 features two synchronous serial ports that
provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at
the full clock rate of the processor, providing each with a maxi-
mum data rate of 40 Mbit/s. Independent transmit and receive
functions provide greater flexibility for serial communications.
Serial port data can be automatically transferred to and from
on-chip memory via DMA. Each of the serial ports offers TDM
multichannel mode.
The serial ports can operate with little-endian or big-endian
transmission formats, with word lengths selectable from three
bits to 32 bits. They offer selectable synchronization and trans-
mit modes as well as optional µ-law or A-law companding.
Serial port clocks and frame syncs can be internally or externally
generated. The serial ports also include keyword and keymask
features to enhance interprocessor communication.
Multiprocessing
The ADSP-21061 offers powerful features tailored to multipro-
cessing DSP systems. The unified address space allows direct
interprocessor accesses of each ADSP-21061’s internal memory.
Distributed bus arbitration logic is included on-chip for simple,
glueless connection of systems containing up to six ADSP-21061s
and a host processor. Master processor changeover incurs only
one cycle of overhead. Bus arbitration is selectable as either
fixed or rotating priority. Bus lock allows indivisible read-modify-
write sequences for semaphores. A vector interrupt is provided
for interprocessor commands. Maximum throughput for inter-
processor data transfer is 500 Mbytes/sec over the external port.
Broadcast writes allow simultaneous transmission of data to
all ADSP-21061s and can be used to implement reflective
semaphores.
Program Booting
The internal memory of the ADSP-21061 can be booted at
system power-up from either an 8-bit EPROM or a host proces-
sor. Selection of the boot source is controlled by the BMS (Boot
Memory Select), EBOOT (EPROM Boot), and LBOOT (Host
Boot) pins. 32-bit and 16-bit host processors can be used for
booting. See the BMS pin in the Pin Function Descriptions
section of this data sheet.
REV. B
–5–
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