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ADSP-21061KS-160 Schematic ( PDF Datasheet ) - Analog Devices

Teilenummer ADSP-21061KS-160
Beschreibung ADSP-2106x SHARC DSP Microcomputer Family
Hersteller Analog Devices
Logo Analog Devices Logo 




Gesamt 30 Seiten
ADSP-21061KS-160 Datasheet, Funktion
a
ADSP-2106x SHARC®
DSP Microcomputer Family
ADSP-21061/ADSP-21061L
SUMMARY
High Performance Signal Computer for Speech, Sound,
Graphics and Imaging Applications
Super Harvard Architecture Computer (SHARC)—
Four Independent Buses for Dual Data, Instructions,
and I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU and Shifter
1 Megabit On-Chip SRAM Memory and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
KEY FEATURES
50 MIPS, 20 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
240-Lead MQFP Package
225-Ball Plastic Ball Grid Array (PBGA)
Pin-Compatible with ADSP-21060 (4 Mbit) and
ADSP-21062 (2 Mbit)
Flexible Data Formats and 40-Bit Extended Precision
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats
32-Bit Fixed-Point Data Format, Integer and Fractional,
with 80-Bit Accumulators
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel with
Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)
1 Megabit Configurable On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Configurable as 32K Words Data Memory (32-Bit), 16K
Words Program Memory (48-Bit) or Combinations of
Both Up to 1 Mbit
Off-Chip Memory Interfacing
4-Gigawords Addressable (32-Bit Address)
Programmable Wait State Generation, Page-Mode DRAM
Support
CORE PROCESSOR
TIMER
INSTRUCTION
CACHE
32 x 48-BIT
DAG1 DAG2
8 x 4 x 32 8 x 4 x 24
PROGRAM
SEQUENCER
PM ADDRESS BUS
24
DM ADDRESS BUS
32
DUAL-PORTED SRAM
TWO INDEPENDENT
DUAL-PORTED BLOCKS
PROCESSOR PORT
ADDR
DATA
ADDR
DATA
I/O PORT
DATA
ADDR
DATA
ADDR
IOD IOA
48 17
JTAG
TEST &
EMULATION
7
EXTERNAL
PORT
ADDR BUS
MUX
32
BUS
CONNECT
(PX)
PM DATA BUS
48
DM DATA BUS 40/32
MULTIPROCESSOR
INTERFACE
DATA BUS
MUX
48
HOST PORT
MULTIPLIER
DATA
REGISTER
FILE
16 x 40-BIT
BARREL
SHIFTER
ALU
IOP
REGISTERS
(MEMORY MAPPED)
CONTROL,
STATUS &
DATA BUFFERS
DMA
CONTROLLER
SERIAL PORTS
(2)
I/O PROCESSOR
Figure 1. ADSP-21061/ADSP-21061L Block Diagram
4
6
6
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000






ADSP-21061KS-160 Datasheet, Funktion
ADSP-21061/ADSP-21061L
ADSP-2106x #6
ADSP-2106x #5
ADSP-2106x #4
3
011
ADSP-2106x #3
CLKIN
ADDR31-0
RESET
DATA47-0
RPBA
I D 2-0
CONTROL
CPA
BR1-2, BR4-6
BR3
5
ADSP-2106x #2
CLKIN
RESET
ADDR31-0
DATA47-0
3
010
RPBA
I D 2-0
CONTROL
1x
CLOCK
RESET
CPA
BR1, BR3-6
BR2
5
3
001
ADSP-2106x #1
CLKIN
RESET
RPBA
I D 2-0
ADDR31-0
DATA47-0
RD
WR
ACK
MS3-0
CONTROL
BMS
PAGE
SBTS
SW
ADRCLK
CS
HBR
HBG
REDY
CPA
BR2-6
BR1
5
ADDR
DATA
GLOBAL
MEMORY
OE AND
WE PERIPHERALS
ACK (OPTIONAL)
CS
CS
ADDR
DATA
BOOT
EPROM
(OPTIONAL)
ADDR
HOST
PROCESSOR
INTERFACE
(OPTIONAL)
DATA
Figure 3. Multiprocessing System
–6– REV. B

6 Page









ADSP-21061KS-160 pdf, datenblatt
ADSP-21061/ADSP-21061L
TARGET BOARD CONNECTOR FOR EZ-ICE PROBE
The ADSP-2106x EZ-ICE Emulator uses the IEEE 1149.1
JTAG test access port of the ADSP-2106x to monitor and control
the target board processor during emulation. The EZ-ICE
probe requires the ADSP-2106x’s CLKIN, TMS, TCK,
TRST, TDI, TDO, EMU, and GND signals be made acces-
sible on the target system via a 14-pin connector (a 2 row × 7
pin strip header) such as that shown in Figure 5. The EZ-ICE
probe plugs directly onto this connector for chip-on-board
emulation. You must add this connector to your target board
design if you intend to use the ADSP-2106x EZ-ICE. The total
trace length between the EZ-ICE connector and the furthest
device sharing the EZ-ICE JTAG pins should be limited to 15
inches maximum for guaranteed operation. This length restric-
tion must include EZ-ICE JTAG signals that are routed to one
or more ADSP-2106x devices, or a combination of ADSP-
2106x devices and other JTAG devices on the chain.
GND
1
2
EMU
KEY (NO PIN)
BTMS
3
5
4
CLKIN (OPTIONAL)
6
TMS
BTCK
7
8
TCK
9 10
BTRST
9
TRST
BTDI
11
12
TDI
GND
13
14
TDO
TOP VIEW
Figure 5. Target Board Connector For ADSP-21061/ADSP-
21061L EZ-ICE Emulator (Jumpers in Place)
The 14-pin, 2-row pin strip header is keyed at the Pin 3 location —
Pin 3 must be removed from the header. The pins must be
0.025 inch square and at least 0.20 inch in length. Pin spacing
should be 0.1 × 0.1 inches. Pin strip headers are available from
vendors such as 3M, McKenzie and Samtec.
The BTMS, BTCK, BTRST and BTDI signals are provided so
the test access port can also be used for board-level testing.
When the connector is not being used for emulation, place
jumpers between the Bxxx pins and the xxx pins. If the test
access port will not be used for board testing, tie BTRST to GND
and tie or pull BTCK up to VDD. The TRST pin must be
asserted after power-up (through BTRST on the connector) or
held low for proper operation of the ADSP-2106x. None of the
Bxxx pins (Pins 5, 7, 9, 11) are connected on the EZ-ICE probe.
The JTAG signals are terminated on the EZ-ICE probe as
follows:
Signal Termination
TMS Driven through 22 Resistor (16 mA Driver)
TCK Driven at 10 MHz through 22 Resistor (16 mA
Driver)
TRST* Active Low Driven through 22 Resistor (16 mA
Driver) (Pulled Up by On-Chip 20 kResistor)
TDI Driven by 22 Resistor (16 mA Driver)
TDO One TTL Load, Split Termination (160/220)
CLKIN One TTL Load, Split Termination (160/220)
EMU Active Low 4.7 kPull-Up Resistor, One TTL Load
(Open-Drain Output from the DSP)
*TRST is driven low until the EZ-ICE probe is turned on by the emulator at
software start-up. After software start-up, TRST is driven high.
Figure 6 shows JTAG scan path connections for systems that
contain multiple ADSP-2106x processors.
ADSP-2106x
#1
JTAG
DEVICE
(OPTIONAL)
ADSP-2106x
#n
TDI TDI
TDO
TDI
TDO
TDI TDO
OTHER
JTAG
CONTROLLER
EZ-ICE
JTAG
CONNECTOR
TCK
TMS
EMU
TRST
TDO
CLKIN
OPTIONAL
Figure 6. JTAG Scan Path Connections for Multiple ADSP-21061/ADSP-21061L Systems
–12–
REV. B

12 Page





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