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ADS931 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS931
Beschreibung 8-Bit/ 30MHz Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 12 Seiten
ADS931 Datasheet, Funktion
®
ADS931E
ADS931
TM 8-Bit, 30MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q +2.7V TO +5.5V SUPPLY OPERATION
q LOW POWER: 69mW at +3V
q ADJUSTABLE FULL SCALE RANGE WITH
EXTERNAL REFERENCE
q NO MISSING CODES
q POWER DOWN
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q BATTERY POWERED EQUIPMENT
q CAMCORDERS
q PORTABLE TEST EQUIPMENT
q DIGITAL CAMERAS
q COMMUNICATIONS
DESCRIPTION
The ADS931 is a high speed pipelined analog-to-
digital converter that is specified to operate from
standard +5V or +3V power supplies. This converter
includes a high bandwidth track/hold and an 8-bit
quantizer. The performance is specified with a single-
ended input range of 1V to 2V when operating off of
a +3V supply. This device also allows for standard
input ranges such as 2V to 4V or 2V to 3V, when
operating on +5V supplies. The full scale input range
is set by an external reference.
The ADS931 employs digital error correction tech-
niques to provide excellent differential linearity for
demanding imaging applications. Its low distortion and
high SNR give the extra margin needed for telecom-
munications, video and test instrumentation applica-
tions. This high performance A/D converter is speci-
fied for performance at a 30MHz sampling rate. The
ADS931 is available in a 28-Lead SSOP package.
ADS931
CLK
Timing
Circuitry
LVDD
IN T/H
Pipeline
A/D
Error
Correction
Logic
3-State
Outputs
8-Bit
Digital
Data
Reference
Ladder
REFT CM REFB
Pwrdn OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1996 Burr-Brown Corporation
PDS-11349C
ADS931Printed in U.S.A. March, 1998
®






ADS931 Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +3V, specified single-ended input (–1dBFS) and sampling rate = 30MHz, unless otherwise specified.
2.0
1.0
0
–1.0
–2.0
0
DIFFERENTIAL LINEARITY ERROR
fIN = 500kHz
64 128 192
Output Code
256
2.0
1.0
0
–1.0
–2.0
0
DIFFERENTIAL LINEARITY ERROR
fIN = 12.5MHz
64 128 192
Output Code
256
4.0
2.0
0
–2.0
–4.0
0
INTEGRAL LINEARITY ERROR
fIN = 500kHz
64 128 192
Output Code
256
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
50
SFDR
48
SNR
46
44
0.1
1 10
Frequency (MHz)
100
100
80
60
40
20
0
–50
SWEPT POWER SFDR
dBFS
dBc
–40 –30 –20 –10
Input Amplitude (dBFS)
0
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
0.9
0.7
0.5
0.3
0.1
–50
–25
fIN = 500kHz
fIN = 12.5MHz
0 25 50
Temperature (°C)
75 100
®
ADS931
6

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ADS931 pdf, datenblatt
duty cycle, along with fast rise and fall times (2ns or less),
are recommended to meet the rated performance specifica-
tions. However, the ADS931 performance is tolerant to duty
cycle variations of as much as ±10%, which should not
affect the performance. For applications operating with
input frequencies up to Nyquist (fCLK/2) or undersampling
applications, special consideration must be made to provide
a clock with very low jitter. Clock jitter leads to aperture
jitter (tA) which can be the ultimate limitation to achieving
good SNR performance. Equation (5) shows the relationship
between aperture jitter, input frequency and the signal-to-
noise ratio:
SNR = 20log10 [1/(2 π fIN tA)]
(5)
DIGITAL OUTPUTS
The digital outputs of the ADS931 are standard CMOS
stages and designed to be compatible to both high speed
TTL and CMOS logic families. The logic thresholds are for
low-voltage CMOS: VOL = 0.4V, VOH = 2.4V, which allows
the ADS931 to directly interface to 3V logic. The digital
output driver of the ADS931 uses a dedicated digital supply
pin (pin 2, LVDD), see Figure 8. By adjusting the voltage on
LVDD, the digital output levels will vary respectively. It is
recommended to limit the fan-out to one in order to keep the
capacitive loading on the data lines below the specified
15pF. If necessary, external buffers or latches may be used
to provide the added benefit of isolating the A/D converter
from any digital activities on the bus coupling back high
frequency noise, which degrades the performance.
SINGLE-ENDED INPUT
+FS (IN = REFT Voltage)
+FS –1LSB
+FS –2LSB
+3/4 Full Scale
+1/2 Full Scale
+1/4 Full Scale
+1LSB
Bipolar Zero (IN +1.5V)
–1LSB
–1/4 Full Scale
–1/2 Full Scale
–3/4 Full Scale
–FS +1LSB
–FS (IN = REFB Voltage)
STRAIGHT OFFSET BINARY
(SOB)
PIN 12
FLOATING or LO
11111111
11111111
11111110
11100000
11000000
10100000
10000001
10000000
01111111
01100000
01000000
00100000
00000001
00000000
TABLE I. Coding Table for the ADS931.
POWER-DOWN MODE
The ADS931’s low power consumption can be reduced even
further by initiating a power-down mode. For this, the Power
Down pin (pin 17) must be tied to a logic “High” reducing
the current drawn from the supply by approximately 84%. In
normal operation, the power-down mode is disabled by an
internal pull-down resistor (50k).
+VS +LVDD
ADS931
Digital
Output
Stage
FIGURE 8. Independent Supply Connection for Output
Stage.
During power-down, the digital outputs are set in 3-state.
With the clock applied, the converter does not accurately
process the sampled signal. After removing the power-down
condition, the output data from the following 5 clock cycles
is invalid (data latency).
DECOUPLING AND GROUNDING
CONSIDERATIONS
The ADS931 has several supply pins, one of which is
dedicated to supply only the output driver (LVDD). The
remaining supply pins are not divided into analog and digital
supply pins (+VS) since they are internally connected on the
chip. For this reason, it is recommended that the converter be
treated as an analog component and to power it only from
the analog supply. Digital supply lines often carry high
levels of noise which can couple back into the converter and
limit performance.
Because of the pipeline architecture, the converter also
generates high frequency transients and noise that are fed
back into the supply and reference lines. This requires that
the supply and reference pins be sufficiently bypassed.
Figure 9 shows the recommended decoupling scheme for the
analog supplies. In most cases, 0.1µF ceramic chip capaci-
tors are adequate to keep the impedance low over a wide
frequency range. Their effectiveness largely depends on the
proximity to the individual supply pin. Therefore, they
should be located as close as possible to the supply pins. In
addition, one larger bipolar capacitor (1µF to 22µF) should
be placed on the PC board in proximity of the converter
circuit.
ADS931
+VS GND
1 13 14
+VS
18
GND
19 20
+VS
28
0.1µF
0.1µF
0.1µF
FIGURE 9. Recommended Bypassing for Analog Supply
Pins.
®
ADS931
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