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ADS8402IBPFBT Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS8402IBPFBT
Beschreibung 16-BIT/ 1.25 MSPS/ UNIPOLAR DIFFERENTIAL INPUT/ MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
Hersteller Burr-Brown Corporation
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Gesamt 25 Seiten
ADS8402IBPFBT Datasheet, Funktion
ADS8402
SLAS154B – DECEMBER 2002 – REVISED MAY 2003
16-BIT, 1.25 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICRO POWER SAMPLING
ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
FEATURES
D 1.25-MHz Sample Rate
D 16-Bit NMC Ensured Over Temperature
D Zero Latency
D Unipolar Differential Input Range: Vref to –Vref
D Onboard Reference
D Onboard Reference Buffer
D High-Speed Parallel Interface
D Power Dissipation: 155 mW at 1.25 MHz Typ
D Wide Digital Supply
D 8-/16-Bit Bus Transfer
D 48-Pin TQFP Package
APPLICATIONS
D DWDM
D Instrumentation
D High-Speed, High-Resolution, Zero Latency
Data Acquisition Systems
D Transducer Interface
D Medical Instruments
D Communication
DESCRIPTION
The ADS8402 is a 16-bit, 1.25 MHz A/D converter with an
internal 4.096-V reference. The device includes a 16-bit
capacitor-based SAR A/D converter with inherent sample
and hold. The ADS8402 offers a full 16-bit interface and an
8-bit option where data is read using two 8-bit read cycles.
The ADS8402 has a unipolar differential input. It is
available in a 48-lead TQFP package and is characterized
over the industrial –40°C to 85°C temperature range.
REFOUT
SAR
+IN
–IN
REFIN
+
_
CDAC
Comparator
4.096-V
Internal
Reference
Clock
Output
Latches
and
3-State
Drivers
Conversion
and
Control Logic
BYTE
16-/8-Bit
Parallel DATA
Output Bus
RESET
CONVST
BUSY
CS
RD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2002–2003, Texas Instruments Incorporated






ADS8402IBPFBT Datasheet, Funktion
ADS8402
SLAS154B DECEMBER 2002 REVISED MAY 2003
www.ti.com
TIMING CHARACTERISTICS
All specifications typical at 40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3)
PARAMETER
MIN TYP
tCONV
tACQ
tpd1
tpd2
tw1
tsu1
tw2
Conversion time
Acquisition time
CONVST low to conversion started (BUSY high)
Propagation delay time, end of conversion to BUSY low
Pulse duration, CONVST low
Setup time, CS low to CONVST low
Pulse duration, CONVST high
CONVST falling edge jitter
600
150
20
0
20
tw3 Pulse duration, BUSY signal low
tw4 Pulse duration, BUSY signal high
th1
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS
16/16 input changes) after CONVST low
Min(tACQ)
40
td1 Delay time, CS low to RD low
tsu2 Setup time, RD high to CS high
tw5 Pulse duration, RD low
ten Enable time, RD low (or CS low for read cycle) to data valid
td2 Delay time, data hold from RD high
td3 Delay time, BUS16/16 or BYTE rising edge or falling edge to data valid
tw6 Pulse duration, RD high time
th2 Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge
tpd4 Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge
tsu3 Setup time, BYTE rising edge to RD falling edge
th3 Hold time, BYTE falling edge to RD falling edge
0
0
50
0
2
20
50
Max(td5)
0
0
tdis Disable time, RD High (CS high for read cycle) to 3-stated data bus
td5 Delay time, BUSY low to MSB data valid delay time
(1) All input signals are specified with tr = tf = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (VIL + VIH)/2.
(2) See timing diagrams.
(3) All timings are measured with 10 pF equivalent loads on all data bits and BUSY pins.
MAX
610
40
20
10
630
30
30
30
0
UNIT
ns
ns
ns
ns
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
6

6 Page









ADS8402IBPFBT pdf, datenblatt
ADS8402
SLAS154B DECEMBER 2002 REVISED MAY 2003
CONVST
tpd1
BUSY
tw1
tw4
tpd2
CS = 0
CONVERT
t(CONV)
tw2
tw3
www.ti.com
t(CONV)
SAMPLING
(When CS = 0)
t(ACQ)
BYTE
RD = 0
DB[15:8]
th1
td5
Previous D [7:0]
tdis
D [15:8]
D [7:0]
th1
td3
Next D [15:8]
DB[7:0]
Signal internal to device
D [7:0]
Next D [7:0]
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGNDAuto Read
CS
RD
BYTE
ten
DB[15:0]
HiZ
Valid
ten
tdis
HiZ
td3
Valid
Valid
Figure 5. Detailed Timing for Read Cycles
tdis
HiZ
12

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ADS8402IBPFBT16-BIT/ 1.25 MSPS/ UNIPOLAR DIFFERENTIAL INPUT/ MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCEBurr-Brown Corporation
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