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PDF ADS8361IDBQR Data sheet ( Hoja de datos )
| Número de pieza | ADS8361IDBQR | |
| Descripción | Dual/ 500kSPS/ 16-Bit/ 2 + 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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ADS8361
ADS8361
ADS8361
SBAS230C – AUGUST 2002 – REVISED SEPTEMBER 2004
Dual, 500kSPS, 16-Bit, 2 + 2 Channel,
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 2 SIMULTANEOUS 16-BIT DACs
q 4 FULLY DIFFERENTIAL INPUT CHANNELS
q 2µs THROUGHPUT PER CHANNEL
q 4µs TOTAL THROUGHPUT FOR FOUR CHANNELS
q LOW POWER: 150mW
q INTERNAL REFERENCE
q FLEXIBLE SERIAL INTERFACE
q 16-BIT UPGRADE TO THE 12-BIT ADS7861
q PIN COMPATIBLE WITH THE ADS7861
APPLICATIONS
q MOTOR CONTROL
q MULTI-AXIS POSITIONING SYSTEMS
q 3-PHASE POWER CONTROL
DESCRIPTION
The ADS8361 is a dual, 16-bit, 500kSPS, Analog-to-Digital
(A/D) converter with four fully differential input channels grouped
into two pairs for high-speed, simultaneous signal acquisition.
Inputs to the sample-and-hold amplifiers are fully differential
and are maintained differentially to the input of the A/D con-
verter. This provides excellent common-mode rejection of
80dB at 50kHz, which is important in high-noise environments.
The ADS8361 offers a high-speed, dual serial interface and
control inputs to minimize software overhead. The output data
for each channel is available as a 16-bit word. The ADS8361
is offered in SSOP-24 and QFN-32 (5x5) packages and is fully
specified over the –40°C to +85°C operating range.
CH A0+
CH A0–
CH A1+
CH A1–
REFIN
REFOUT
CH B0+
CH B0–
SHA
CDAC
SAR
COMP
Internal
2.5V
Reference
SHA
CDAC
COMP
Serial
Interface
SERIAL DATA A
SERIAL DATA B
M0
M1
A0
CLOCK
CS
RD
BUSY
CONVST
CH B1+
CH B1–
SAR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002-2004, Texas Instruments Incorporated
1 page  
BASIC CIRCUIT CONFIGURATION
+
10µF
0.1µF
ADS8361
1 BGND
2 CH B1+
3 CH B1–
4 CH B0+
5 CH B0–
6 CH A1+
7 CH A1–
8 CH A0+
9 CH A0–
10 REFIN
11 REFOUT
12 AGND
BVDD 24
SERIAL DATA A 23
SERIAL DATA B 22
BUSY 21
CLOCK 20
CS 19
RD 18
CONVST 17
A0 16
M0 15
M1 14
AVDD 13
+
10µF
0.1µF
+2.7V to +5.5V Digital Supply
+
10µF
BUSY Output
Clock Input
Chip Select
Read Input
Conversion Start
A0 Address Select
M0 Address Select
M1 Address Select
+5V Analog Supply
0.1µF
TRUTH TABLE
M0 M1 A0
000
001
010
011
10X
11X
NOTE: X = Don’t Care.
TWO-CHANNEL/FOUR-CHANNEL OPERATION
Two-Channel
Two-Channel
Two-Channel
Two-Channel
Four-Channel
Four-Channel
DATA ON SERIAL OUTPUTS
A and B
A and B
A Only
A Only
A and B
A Only
CHANNELS CONVERTED
A0 and B0
A1 and B1
A0 and B0
A1 and B1
Sequential
Sequential
ADS8361
SBOS230C
www.ti.com
5
5 Page 
CM + VREF
CM Voltage
+VREF
CM – VREF
+IN
–VREF
–IN = CM Voltage
Single-Ended Inputs
t
CM + 1/2 VREF
CM Voltage
CM – 1/2 VREF
+IN +VREF
–IN
–VREF
Differential Inputs
t
(+IN) + (–IN)
NOTES: Common-Mode Voltage (Differential Mode) =
, Common-Mode Voltage (Single-Ended Mode) = IN–.
2
The maximum differential voltage between +IN and –IN of the ADS8361 is VREF. See Figures 3 and 4 for a further
explanation of the common voltage range for single-ended and differential inputs.
FIGURE 2. Using the ADS8361 in the Single-Ended and Differential Input Modes.
5
4.1
4
AVDD = 5V
5
4.7
4
AVDD = 5V
4.0
3
Single-Ended Input
2
2.7
2.3
3 Differential Input
2
1 0.9
0
1
0.3
0
1.0
–1
1.2
1.0
2.0
VREF (V)
2.6
2.5
3.0
FIGURE 3. Single-Ended Input: Common-Mode Voltage
Range vs VREF.
In each case, care should be taken to ensure that the output
impedance of the sources driving the +IN and –IN inputs are
matched. Otherwise, this may result in offset error, gain error,
and linearity error which will change with both temperature
and input voltage.
The input current on the analog inputs depend on a number
of factors: sample rate, input voltage, and source impedance.
Essentially, the current into the ADS8361 charges the inter-
nal capacitor array during the sampling period. After this
–1
1.0
1.2
2.0
VREF (V)
2.6
2.5
3.0
FIGURE 4. Differential Input: Common-Mode Voltage
Range vs VREF.
capacitance has been fully charged, there is no further input
current. The source of the analog input voltage must be able
to charge the input capacitance (25pF) to a 16-bit settling
level within 4 clock cycles. When the converter goes into the
hold mode, the input impedance is greater than 1GΩ.
Care must be taken regarding the absolute analog input
voltage. The +IN and –IN inputs should always remain within
the range of AGND – 0.3V to AVDD + 0.3V.
ADS8361
SBOS230C
www.ti.com
11
11 Page | ||
| Páginas | Total 23 Páginas | |
| PDF Descargar | [ Datasheet ADS8361IDBQR.PDF ] | |
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| ADS8361IDBQ | Dual/ 500kSPS/ 16-Bit/ 2 + 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | Burr-Brown Corporation |
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