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ADS8325IDGKT Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS8325IDGKT
Beschreibung 16-Bit/ High-Speed/ 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 21 Seiten
ADS8325IDGKT Datasheet, Funktion
ADS8325
ADS8325
ADS8325
SBAS226A – MARCH 2002 – REVISED JUNE 2003
16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
q 16-BITS NO MISSING CODES
q VERY LOW NOISE: 3LSBp-p
q EXCELLENT LINEARITY: ±1.5LSB typ
q microPOWER: 4.5mW at 100kHz
1mW at 10kHz
q MSOP-8 AND SON-8 PACKAGES
(SON Package Size Same as 3x3 QFN)
q 16-BIT UPGRADE TO THE 12-BIT ADS7816
AND ADS7822
q PIN-COMPATIBLE WITH THE ADS7816,
ADS7822, ADS7826, ADS7827, ADS7829, AND
ADS8320
q SERIAL (SPI/SSI) INTERFACE
APPLICATIONS
q BATTERY-OPERATED SYSTEMS
q REMOTE DATA ACQUISITION
q ISOLATED DATA ACQUISITION
q SIMULTANEOUS SAMPLING, MULTI-CHANNEL
SYSTEMS
q INDUSTRIAL CONTROLS
q ROBOTICS
q VIBRATION ANALYSIS
The ADS8325 is a 16-bit, sampling, Analog-to-Digital (A/D)
converter specified for a supply voltage range from 2.7V to
5.5V. It requires very little power, even when operating at the
full 100kHz data rate. At lower data rates, the high speed of
the device enables it to spend most of its time in the power-
down mode. For example, the average power dissipation is
less than 1mW at a 10kHz data rate.
The ADS8325 offers excellent linearity and very low noise
and distortion. It also features a synchronous serial (SPI/SSI
compatible) interface and a differential input. The reference
voltage can be set to any level within the range of 2.5V to
VDD.
Low power and small size make the ADS8325 ideal for
portable and battery-operated systems. It is also a perfect fit
for remote data acquisition modules, simultaneous multi-
channel systems, and isolated data acquisition. The ADS8325
is available in MSOP-8 and SON-8 packages.
The SON package size is the same as a 3x3 QFN package.
SAR
REF
+IN
IN
ADS8325
S/H Amp
CDAC
Comparator
Serial
Interface
DOUT
DCLOCK
CS/SHDN
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002-2003, Texas Instruments Incorporated






ADS8325IDGKT Datasheet, Funktion
TIMING DIAGRAMS
Timing Diagrams and Test Circuits for the Parameters in the Timing Characteristics table.
CS/SHDN
DCLOCK
DOUT
tSUCS
Sample
Complete Cycle
Conversion
Power Down
tCSD
Hi-Z
tSMPL
Use positive clock edge for data transfer
0 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
(MSB)
(LSB)
tCONV
Hi-Z
NOTE: A minimum of 22 clock cycles are required for 16-bit conversion. Shown are 24 clock cycles.
If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again.
1.4V
DOUT
3k
100pF
CLOAD
Test Point
Load Circuit for tdDO, tr, and tf
DCLOCK
tdDO
DOUT
thDO
Voltage Waveforms for DOUT Delay Times, tdDO
DOUT
tr
90%
10%
tf
Voltage Waveforms for DOUT Rise and Fall Times, tr, tf
Test Point
DOUT
3k
100pF
CLOAD
VCC
tdis Waveform 2, ten
tdis Waveform 1
Load Circuit for tdis and ten
CS/SHDN
90%
DOUT
Waveform 1(1)
DOUT
Waveform 2(2)
90%
tdis
10%
Voltage Waveforms for tdis
NOTES: (1) Waveform 1 is for an output with internal
conditions such that the output is HIGH unless disabled by the
output control. (2) Waveform 2 is for an output with internal
conditions such that the output is LOW unless disabled by the
output control.
TIMING CHARACTERISTICS
SYMBOL
tSMPL
tCONV
tCYC
tCSD
tSUCS
tHDO
tDIS
tEN
tF
tR
DESCRIPTION
Analog Input Sample Time
Conversion Time
Throughput Rate
CS Falling to DCLOCK LOW
CS Falling to DCLOCK Rising
DCLOCK Falling to Current DOUT Not Valid
CS Rising to DOUT Tri-State
DCLOCK Falling to DOUT Enabled
DOUT Fall Time
DOUT Rise Time
CS/SHDN
DCLOCK
DOUT
MIN
4.5
20
5
6 www.ti.com
145
ten
Voltage Waveforms for ten
B15
TYP
16
15
70
20
5
7
MAX
5.0
100
0
100
50
25
25
UNITS
Clk Cycles
Clk Cycles
kHz
ns
ns
ns
ns
ns
ns
ns
ADS8325
SBAS226A

6 Page









ADS8325IDGKT pdf, datenblatt
1
0.5
0
0.3
VDD = 5V
1
2 2.5 3
4
VREF (V)
4.8 5
6
FIGURE 3. +IN Analog Input: Common-Mode Voltage Range
vs VREF.
Care must be taken regarding the absolute analog input
voltage. To maintain the linearity of the converter, the IN
input should not drop below GND 0.3V or exceed
GND + 0.5V. The +IN input should always remain within the
range of GND 0.3V to VDD + 0.3V, or IN to IN + VREF,
whichever limit is reached first. Outside of these ranges, the
converters linearity may not meet specifications.
To minimize noise, low bandwidth input signals with low-
pass filters should be used. In each case, care should be
taken to ensure that the output impedance of the sources
driving the +IN and IN inputs are matched. Often, a small
capacitor (20pF) between the positive and negative inputs
helps to match their impedance. To obtain maximum perfor-
mance from the ADS8325, the input circuit from Figure 4 is
recommended.
CHANGE IN GAIN vs COMMON-MODE VOLTAGE
60
50 VDD = 5V
VREF = 4V
40
30
20
10
0
10
0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VCM (V)
FIGURE 5. Change in Gain vs Common-Mode Voltage.
CHANGE IN UPO vs COMMON-MODE VOLTAGE
30
VDD = 5V
VREF = 4V
20
10
0
10
20
0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
VCM (V)
FIGURE 6. Change in Unipolar Offset vs Common-Mode
Voltage.
OPA340
50
+IN
100pF
2020pF
ADS8325
IN 2020pF
OPA340
OPA340
50+IN 2020pF
100pF
1nF ADS8325
50
100pF
IN
2020pF
Single-Ended
FIGURE 4. Single-Ended and Differential Methods of Interfacing the ADS8325.
Differential
12
www.ti.com
ADS8325
SBAS226A

12 Page





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