PDF ADS8323 Data sheet ( Hoja de datos )

Número de pieza	ADS8323
Descripción	16-Bit/ 500kSPS/ microPower Sampling ANALOG-TO-DIGITAL CONVERTER
Fabricantes	Burr-Brown Corporation
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No Preview Available ! ADS8323 ® ADS8323 SBAS224B – DECEMBER 2001 – REVISED MAY 2002 16-Bit, 500kSPS, microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q HIGH-SPEED PARALLEL INTERFACE q 500kSPS SAMPLING RATE q LOW POWER: 85mW at 500kSPS q BIPOLAR INPUT RANGE q TQFP-32 PACKAGE APPLICATIONS q HIGH-SPEED DATA AQUISITION q OPTICAL POWER MONITORING q MOTOR CONTROL q ATE DESCRIPTION The ADS8323 is a 16-bit, 500kSPS Analog-to-Digital Con- verter (ADC) with an internal 2.5V reference. The device includes a 16-bit capacitor-based SAR ADC with inherent sample-and-hold. The ADS8323 offers a full 16-bit interface, or an 8-bit option where data is read using two read cycles. The ADS8323 is available in a TQFP-32 package and is specified over the industrial –40°C to +85°C temperature range. SAR +IN –IN REFIN REFOUT ADS8323 S/H Amp CDAC Comparator Internal +2.5V Ref Output Latches and Three State Drivers BYTE Parallel Data Output Conversion and Control Logic CLOCK CONVST CS RD BUSY Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com Copyright © 2001, Texas Instruments Incorporated 1 page PIN CONFIGURATION Top View 32 31 30 29 28 27 26 25 DB15 1 DB14 2 DB13 3 DB12 4 DB11 5 DB10 6 DB9 7 DB8 8 ADS8323 24 CS 23 BYTE 22 RD 21 CONVST 20 CLOCK 19 DGND 18 +DVDD 17 BUSY 9 10 11 12 13 14 15 16 TQFP PIN ASSIGNMENTS PIN NAME I/O DESCRIPTION 1 DB15 DO Data Bit 15 - MSB 2 DB14 DO Data Bit 14 3 DB13 DO Data Bit 13 4 DB12 DO Data Bit 12 5 DB11 DO Data Bit 11 6 DB10 DO Data Bit 10 3 DB9 DO Data Bit 9 8 DB8 DO Data Bit 8 9 DB7 DO Data Bit 7 10 DB6 DO Data Bit 6 11 DB5 DO Data Bit 5 12 DB4 DO Data Bit 4 13 DB3 DO Data Bit 3 14 DB2 DO Data Bit 2 15 DB1 DO Data Bit 1 16 DB0 DO Data Bit 0 - LSB 17 BUSY DO HIGH when a conversion is in progress. 18 +DVDD P Digital Power Supply, +5VDC. PIN NAME I/O DESCRIPTION 19 DGND P Digital Ground 20 CLOCK DI An external CMOS compatible clock can be applied to the CLOCK input to synchronize the conversion process to an external source. 21 CONVST DI Convert Start, Active LOW. 22 RD DI Synchronization pulse for the parallel output, Active LOW. 23 BYTE DI Selects 8 most significant bits (LOW) or 8 least significant bits (HIGH). Data valid on pins 9-16. 24 CS DI Chip Select, Active LOW. 25 –IN AI Inverting Input Channel 26 +IN AI Noninverting Input Channel 27 AGND P Analog Ground 28 +AVDD P Analog Power Supply, +5VDC. 29 NC — No Connect 30 NC — No Connect 31 REFIN AI Reference Input. When using the internal 2.5V reference tie this pin directly to REFOUT. 32 REFOUT AO Reference Output NOTE: AI is Analog Input, AO is Analog Output, DI is Digital Input, DO is Digital Output, and P is Power-Supply Connection. ADS8323 SBAS224B www.ti.com 5 5 Page NOISE Figure 6 shows the transition noise of the ADS8323. A low- level DC input was applied to the analog-input pins and the converter was put through 8192 conversions. The digital output of the ADC will vary in output code due to the internal noise of the ADS8323. This is true for all 16-bit SAR-type ADCs. The ADS8323, with five output codes for the σ distribu- tion, will yield a < ±0.8LSB transition noise at 5V operation. Remember that to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. 5052 1968 300 54 818 0014 0015 0016 Code 0017 0018 FIGURE 6. Histogram of 8192 Conversions of a Low-Level DC Input. AVERAGING Averaging the digital codes can compensate the noise of the ADC. By averaging conversion results, transition noise will be reduced by a factor of 1/√n, where n is the number of averages. For example, averaging 4 conversion results will reduce the transition noise by 1/2 to ±0.4LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging—for every decimation by 2, the signal-to-noise ratio will improve 3dB. BIPOLAR INPUTS The differential inputs of the ADS8323 were designed to accept bipolar inputs (–VREF and +VREF) around the common-mode voltage, which corresponds to a 0V to 5V input range with a 2.5V reference. By using a simple op amp circuit featuring four high-precision external resistors, the ADS8323 can be config- ured to accept bipolar inputs. The conventional ±2.5V, ±5V, and ±10V input ranges could be interfaced to the ADS8323 using the resistor values shown in Figure 7. R1 4kΩ Bipolar Input 20kΩ OPA132 R2 OPA353 BIPOLAR INPUT ±10V ±5V ±2.5V R1 1kΩ 2kΩ 4kΩ R2 5kΩ 10kΩ 20kΩ +IN (pin 26) –IN (pin 25) ADS8323 REFOUT (pin 32) 2.5V FIGURE 7. Level Shift Circuit for Bipolar Input Ranges. DIGITAL INTERFACE TIMING AND CONTROL See the timing diagram in the Timing Characteristics section for detailed information on timing signals and their requirements. The ADS8323 uses an external clock (CLOCK, pin 20) that controls the conversion rate of the CDAC. With a 10MHz external clock, the ADC sampling rate is 500kSPS that corresponds to a 2µs maximum throughput time. EXPLANATION OF CLOCK, BUSY AND BYTE PINS CLOCK—An external clock must be provided for the ADS8323. The maximum clock frequency is 10MHz and that provides 500kSPS throughput. The minimum clock frequency is 25kHz and that provides 1.25kHz throughput. The mini- mum clock cycle is 100ns (see Timing Diagram, tC1), and CLOCK must remain HIGH (see Timing Diagram, tW1) or LOW (see Timing Diagram, tW2) for at least 40ns. BUSY—Initially BUSY output is LOW. Reading data from output register or sampling the input analog signal will not affect the state of the BUSY signal. After the CONVST input goes LOW and conversion starts, a maximum of 25ns later the BUSY output will go HIGH. That signal will stay HIGH during conversion and will provide the status of the internal ADC to the DSP or uC. At the end of conversion, on the rising edge of 17th clock cycle, new data from the internal ADC is latched into the output registers. The BUSY signal will go LOW a maximum of 25ns later (see Timing Diagram, tD4). BYTE—The output data will appear as a full 16-bit word on DB15-DB0 (MSB-LSB or D15-D0) if BYTE is LOW. If there is only an 8-bit bus available on a board, the result may also be read on an 8-bit bus by using only DB7-DB0. In this case, two reads are necessary (see Timing Diagram). The first, as before, leaving BYTE LOW and reading the 8 least significant bits on DB7-DB0, then bringing BYTE HIGH. When BYTE is HIGH, the upper 8 bits (D15-D8) will appear on DB7-DB0. ADS8323 SBAS224B www.ti.com 11 11 Page

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