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ADS8320E Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS8320E
Beschreibung 16-Bit/ High-Speed/ 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 13 Seiten
ADS8320E Datasheet, Funktion
® ADS8320
For most current data sheet and other product
information, visit www.burr-brown.com
16-Bit, High-Speed, 2.7V to 5V microPower Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 100kHz SAMPLING RATE
q MICRO POWER:
1.8mW at 100kHz and 2.7V
0.3mW at 10kHz and 2.7V
q POWER DOWN: 3µA max
q MSOP-8 PACKAGE
q PIN-COMPATIBLE TO ADS7816 AND
ADS7822
q SERIAL (SPI/SSI) INTERFACE
APPLICATIONS
q BATTERY OPERATED SYSTEMS
q REMOTE DATA ACQUISITION
q ISOLATED DATA ACQUISITION
q SIMULTANEOUS SAMPLING,
MULTI-CHANNEL SYSTEMS
q INDUSTRIAL CONTROLS
q ROBOTICS
q VIBRATION ANALYSIS
DESCRIPTION
The ADS8320 is a 16-bit sampling analog-to-digital
converter (A/D) with guaranteed specifications over a
2.7V to 5.25V supply range. It requires very little
power even when operating at the full 100kHz data
rate. At lower data rates, the high speed of the device
enables it to spend most of its time in the power-down
mode—the average power dissipation is less than
100µW at 10kHz data rate.
The ADS8320 also features operation from 2.0V to
5.25V, a synchronous serial (SPI/SSI compatible) in-
terface, and a differential input. The reference voltage
can be set to any level within the range of 500mV to
VCC.
Ultra-low power and small size make the ADS8320
ideal for portable and battery-operated systems. It is
also a perfect fit for remote data acquisition mod-
ules, simultaneous multi-channel systems, and iso-
lated data acquisition. The ADS8320 is available in
an MSOP-8 package.
VREF
+In
–In
S/H Amp
SAR
CDAC
Comparator
Control
Serial
Interface
DOUT
DCLOCK
CS/SHDN
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1999 Burr-Brown Corporation
PDS-1504C
Printed in U.S.A. May, 2000






ADS8320E Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, fCLK = 24 • fSAMPLE, unless otherwise specified.
CHANGE IN OFFSET vs REFERENCE VOLTAGE
6
5
VCC = 5V
4
3
2
1
0
–1
–2
–3
1
234
Reference Voltage (V)
5
CHANGE IN OFFSET vs TEMPERATURE
3
2
5V
1
0 2.7V
–1
–2
–3
–50
–25
0 25 50
Temperature (°C)
75
100
CHANGE IN GAIN vs REFERENCE VOLTAGE
5
VCC = 5V
4
3
2
1
0
–1
–2
1
234
Reference Voltage (V)
5
0
–20
–40
–60
–80
–100
–120
–140
0
FREQUENCY SPECTRUM
(8192 Point FFT, FIN = 10.120kHz, –0.3dB)
10 20 30 40
Frequency (kHz)
50
6
4
2
0
–2
–4
–6
–50
CHANGE IN GAIN vs TEMPERATURE
5V
2.7V
–25 0
25 50 75
Temperature (°C)
100
PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE
10
9 VCC = 5V
8
7
6
5
4
3
2
1
0
0.1
1
Reference Voltage (V)
10
®
ADS8320
6

6 Page









ADS8320E pdf, datenblatt
1000
TA = 25°C
fCLK = 2.4MHz
100
VCC = 5.0V
VREF = 5.0V
10
VCC = 2.7V
VREF = 2.5V
1
0.1
1 10
Sample Rate (kHz)
100
FIGURE 5. Maintaining fCLK at the Highest Possible Rate
Allows Supply Current to Drop Linearly with
Sample Rate.
1000
100
10
1
0.1
TA = 25°C
VCC = 5.0V
VREF = 5.0V
fCLK = 24 • fSAMPLE
1 10
Sample Rate (kHz)
100
FIGURE 6. Scaling fCLK Reduces Supply Current Only
Slightly with Sample Rate.
1000
800
600
TA = 25°C
VCC = 5.0V
VREF = 5.0V
fCLK = 24 • fSAMPLE
400
CS LOW (GND)
200
0.0
0.250
0.00
0.1
CS HIGH (VCC)
1 10
Sample Rate (kHz)
100
FIGURE 7. Shutdown Current with CS HIGH is 50nA
Typically, Regardless of the Clock. Shutdown
Current with CS LOW Varies with Sample
Rate.
Figure 5 shows the current consumption of the ADS8320
versus sample rate. For this graph, the converter is clocked
at 2.4MHz regardless of the sample rate—CS is HIGH for
the remaining sample period. Figure 6 also shows current
consumption versus sample rate. However, in this case, the
DCLOCK period is 1/24th of the sample period—CS is
HIGH for one DCLOCK cycle out of every 16.
There is an important distinction between the power-down
mode that is entered after a conversion is complete and the
full power-down mode which is enabled when CS is HIGH.
CS LOW will shut down only the analog section. The digital
section is completely shutdown only when CS is HIGH.
Thus, if CS is left LOW at the end of a conversion and the
converter is continually clocked, the power consumption
will not be as low as when CS is HIGH. See Figure 7 for
more information.
Power dissipation can also be reduced by lowering the
power supply voltage and the reference voltage. The
ADS8320 will operate over a VCC range of 2.0V to 5.25V.
However, at voltages below 2.7V, the converter will not run
at a 100kHz sample rate. See the typical performance curves
for more information regarding power supply voltage and
maximum sample rate.
SHORT CYCLING
Another way of saving power is to utilize the CS signal to
short cycle the conversion. Because the ADS8320 places the
latest data bit on the DOUT line as it is generated, the
converter can easily be short cycled. This term means that
the conversion can be terminated at any time. For example,
if only 14 bits of the conversion result are needed, then the
conversion can be terminated (by pulling CS HIGH) after
the 14th bit has been clocked out.
This technique can be used to lower the power dissipation
(or to increase the conversion rate) in those applications
where an analog signal is being monitored until some con-
dition becomes true. For example, if the signal is outside a
predetermined range, the full 16-bit conversion result may
not be needed. If so, the conversion can be terminated after
the first n bits, where n might be as low as 3 or 4. This results
in lower power dissipation in both the converter and the rest
of the system, as they spend more time in the power-down
mode.
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS8320 circuitry. This will be
particularly true if the reference voltage is low and/or the
conversion rate is high. At a 100kHz conversion rate, the
ADS8320 makes a bit decision every 416ns. That is, for each
subsequent bit decision, the digital output must be updated
with the results of the last bit decision, the capacitor array
appropriately switched and charged, and the input to the
comparator settled to a 16-bit level all within one clock
cycle.
®
ADS8320
12

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