Datenblatt-pdf.com


ADS824 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS824
Beschreibung 10-Bit/ 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 12 Seiten
ADS824 Datasheet, Funktion
®
ADS824E
ADS824
TM 10-Bit, 70MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q HIGH SNR: 59dB
q HIGH SFDR: 70dB
q LOW POWER: 315mW
q INTERNAL/EXTERNAL REFERENCE
OPTION
q SINGLE-ENDED OR DIFFERENTIAL
ANALOG INPUT
q PROGRAMMABLE INPUT RANGE:
1Vp-p or 2Vp-p
q LOW DNL: 0.3LSB
q SINGLE +5V SUPPLY OPERATION
q +3V DIGITAL OUTPUT CAPABILITY
q POWER DOWN: 20mW
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q MEDICAL IMAGING
q HDTV VIDEO DIGITIZING
q COMMUNICATIONS
q TEST EQUIPMENT
+VS
ADS824
DESCRIPTION
The ADS824 is a pipeline, CMOS analog-to-digital converter
that operates from a single +5V power supply. This converter
provides excellent performance with a single-ended input and
can be operated with a differential input for added spurious
performance. This high performance converter includes a 10-bit
quantizer, high bandwidth track/hold, and a high accuracy
internal reference. It also allows for the user to disable the
internal reference and utilize external references. This external
reference option provides excellent gain and offset matching
when used in multi-channel applications or in applications
where full scale range adjustment is required.
The ADS824 employs digital error correction techniques to
provide excellent differential linearity for demanding imaging
applications. Its low distortion and high SNR give the extra
margin needed for medical imaging, communications, video,
and test instrumentation. The ADS824 offers power dissipa-
tion of 315mW and also provides a power-down mode, thus
reducing power dissipation to only 20mW.
The ADS824 is specified at a maximum sampling frequency of
70MHz and a single-ended input range of 1.5V to 3.5V. The
ADS824 is available in a 28-lead SSOP package and is pin
compatible with the 10-bit, 40MHz ADS822 and the 10-bit,
60MHz ADS823.
CLK
VDRV
Timing
Circuitry
VIN IN
IN T/H
10-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D9
CM Internal
Reference
Optional External
Reference
Int/Ext
PD OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1403C
Printed in U.S.A. April, 1999






ADS824 Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 70MHz, external reference, unless otherwise noted.
0
–20
–40
–60
–80
–100
0
UNDERSAMPLING
(Differential Input, 2Vp-p)
fS = 41MHz
fIN = 75MHz
SNR = 58.6dBFS
SFDR = 67dBFS
5.13
10.25
15.38
Frequency (MHz)
20.5
TWO-TONE INTERMODULATION DISTORTION
(Differential Input, 2Vp-p)
0
f1 = 9.5MHz at –7dBFS
f2 = 9.9MHz at –7dBFS
–20 IMD (3) = –63.4dBc
–40
–60
–80
–100
0
8.75
17.50
26.25
Frequency (MHz)
35
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
65
75
SFDR
70
65
SNR
60
55
0.1
1 10
Frequency (MHz)
100
SIGNAL-TO-(NOISE + DISTORTION)
vs TEMPERATURE
65
60
fIN = 10MHz
55
50
–50
–25
fIN = 20MHz
0 25 50
Temperature (°C)
75 100
DYNAMIC PERFORMANCE vs TEMPERATURE
75
SFDR (fIN = 10MHz)
70
65 SFDR (fIN = 20MHz)
SNR (fIN = 10MHz)
60
55
–50
SNR (fIN = 20MHz)
–25 0
25 50
Temperature (°C)
75 100
DIFFERENTIAL LINEARITY ERROR
vs TEMPERATURE
0.35
fIN = 10MHz
0.3
0.25
0.20
–50
–25
0 25 50
Temperature (°C)
75 100
®
ADS824
6

6 Page









ADS824 pdf, datenblatt
given by the following equation. If this value is near your
system requirements, input clock jitter must be reduced.
Jitter SNR = 20 log 1 rms signal to rms noise
2πƒ IN tA
where: ƒIN is input signal frequency
tA is rms clock jitter
Special consideration should be given to clock jitter, particu-
larly in undersampling applications. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of performance. When
digitizing at high sampling rates, the clock should have 50%
duty cycle (tH = tL), along with fast rise and fall times of 2ns
or less.
Digital Outputs
The output data format of the ADS824 is in positive Straight
Offset Binary code, see Tables I and II. This format can
easily be converted into the Binary Two’s Complement code
by inverting the MSB.
It is recommended to keep the capacitive loading on the data
lines as low as possible (15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS824 and affect the performance. If
necessary, external buffers or latches close to the converter’s
output pins may be used to minimize the capacitive loading.
They also provide the added benefit of isolating the ADS824
from any digital noise activities on the bus coupling back
high frequency noise.
SINGLE-ENDED INPUT
(IN = CMV)
+FS –1LSB (IN = REFT)
+1/2 Full Scale
Bipolar Zero (IN = CMV)
–1/2 Full Scale
–FS (IN = REFB)
STRAIGHT OFFSET BINARY
(SOB)
11 1111 1111
11 0000 0000
10 0000 0000
01 0000 0000
00 0000 0000
TABLE I. Coding Table for Single-Ended Input Configura-
tion with IN Tied to the Common-Mode Voltage
(CMV).
+5V or +3V, the ADS824 produces corresponding logic
levels and can directly interface to the selected logic family.
The output stages are designed to supply sufficient current to
drive a variety of logic families. However, it is recom-
mended to use the ADS824 with +3V logic supply. This will
lower the power dissipation in the output stages due to the
lower output swing and reduce current glitches on the supply
line, which may affect the ac performance of the converter.
In some applications, it might be advantageous to decouple
the VDRV pin with additional capacitors or a pi-filter.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS824 should be treated
as an analog component. Whenever possible, the supply pins
should be powered by the analog supply. This will ensure
the most consistent results since digital supply lines often
carry high levels of noise which otherwise would be coupled
into the converter and degrade the achievable performance.
All ground connections on the ADS824 are internally joined
together, obviating the design of split ground planes. The
ground pins (1, 16, 26) should directly connect to an analog
ground plane, which covers the PC board area around the
converter. While designing the layout, it is important to keep
the analog signal traces separated from any digital lines to
prevent noise coupling onto the analog signal path. Because
of its high sampling rate the, ADS824 generates high fre-
quency current transients and noise (clock feedthrough) that
are fed back into the supply and reference lines. This
requires that all supply and reference pins be sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS824. In most cases, 0.1µF ceramic chip
capacitors at each pin are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger bipolar capacitor (1µF to
22µF) should be placed on the PC board in proximity of the
converter circuit.
DIFFERENTIAL INPUT
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full Scale
Bipolar Zero (IN = IN = CMV)
–1/2 Full Scale
–FS (IN = +2V, IN = +3V)
STRAIGHT OFFSET BINARY
(SOB)
11 1111 1111
11 0000 0000
10 0000 0000
01 0000 0000
00 0000 0000
TABLE II. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Range.
Digital Output Driver (VDRV)
The ADS824 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. By setting the voltage at VDRV to
ADS824
+VS
GND
+VS
GND VDRV
27
26 15
16 28
0.1µF
0.1µF 0.1µF
10µF
+
+5V +3/+5V
FIGURE 9. Recommended Bypassing for the Supply Pins.
®
ADS824
12

12 Page





SeitenGesamt 12 Seiten
PDF Download[ ADS824 Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
ADS82010-Bit/ 20MHz Sampling ANALOG-TO-DIGITAL CONVERTERBurr-Brown Corporation
Burr-Brown Corporation
ADS82010-Bit 20MHz Sampling Analog-To-Digital Converter (Rev. B)Texas Instruments
Texas Instruments
ADS82012.2V to 5.5V Low-Power 12-Bit 100kSPS 8-Ch Data Acq System with PGA and SPI (Rev. B)Texas Instruments
Texas Instruments
ADS820E10-Bit/ 20MHz Sampling ANALOG-TO-DIGITAL CONVERTERBurr-Brown Corporation
Burr-Brown Corporation
ADS820U10-Bit/ 20MHz Sampling ANALOG-TO-DIGITAL CONVERTERBurr-Brown Corporation
Burr-Brown Corporation

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche