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ADS822E Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS822E
Beschreibung 10-Bit/ 40MHz Sampling ANALOG-TO-DIGITAL CONVERTERS
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 12 Seiten
ADS822E Datasheet, Funktion
®
ADS825
ADS822
ADS822
ADS825
For most current data sheet and other product
information, visit www.burr-brown.com
TM 10-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTERS
FEATURES
q HIGH SNR: 60dB
q HIGH SFDR: 72dBFS
q LOW POWER: 190mW
q INTERNAL/EXTERNAL REFERENCE OPTION
q SINGLE-ENDED OR
FULLY DIFFERENTIAL ANALOG INPUT
q PROGRAMMABLE INPUT RANGE
q LOW DNL: 0.5LSB
q SINGLE +5V SUPPLY OPERATION
q +3V OR +5V LOGIC I/O COMPATIBLE (ADS825)
q POWER DOWN: 20mW
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q MEDICAL IMAGING
q TEST EQUIPMENT
q COMPUTER SCANNERS
q COMMUNICATIONS
q VIDEO DIGITIZING
DESCRIPTION
The ADS822 and ADS825 are pipeline, CMOS analog-to-digital
converters that operate from a single +5V power supply. These
converters provide excellent performance with a single-ended
input and can be operated with a differential input for added
spurious performance. These high-performance converters in-
clude a 10-bit quantizer, high-bandwidth track-and-hold, and a
high-accuracy internal reference. They also allow for the user to
disable the internal reference and utilize external references. This
external reference option provides excellent gain and offset
matching when used in multi-channel applications or in applica-
tions where full-scale range adjustment is required.
The ADS822 and ADS825 employ digital error correction tech-
niques to provide excellent differential linearity for demanding
imaging applications. Its low distortion and high SNR give the
extra margin needed for medical imaging, communications,
video, and test instrumentation. The ADS822 and ADS825 offer
power dissipation of 190mW and also provide a power-down
mode, thus reducing power dissipation to only 20mW. The
ADS825 is +3V or +5V Logic I/O compatible.
The ADS822 and ADS825 are specified at a maximum sampling
frequency of 40MHz and a single-ended input range of 1.5V to
3.5V. The ADS822 and ADS825 are available in a 28-lead SSOP
package and are pin-for-pin compatible with the 10-bit, 60MHz
ADS823 and ADS826, and the 10-bit, 70MHz ADS824, provid-
ing an upgrade path to higher sampling frequencies.
+VS CLK VDRV
ADS822
ADS825
Timing
Circuitry
VIN IN
IN T/H
10-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D9
CM Internal
Reference
Optional External
Reference
Int/Ext
PD OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1385E
Printed in U.S.A. October, 1999






ADS822E Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = full specified temperature range, VS = +5V, single-ended input range = 1.5V to 3.5V, and sampling rate = 40MHz, external reference, unless otherwise noted.
0
–20
–40
–60
–80
–100
0
UNDERSAMPLING
(Differential Input, 2Vp-p)
fS = 40MHz
fIN = 75MHz
SNR = 59dBFS
SFDR = 66dBFS
5 10 15
Frequency (MHz)
20
TWO-TONE INTERMODULATION DISTORTION
0
f1 = 9.5MHz at –7dBFS
f2 = 9.9MHz at –7dBFS
–20 IMD (3) = –67dB
–40
–60
–80
–100
0
5 10 15
Frequency (MHz)
20
1.0
0.5
0
–0.5
–1.0
0
DIFFERENTIAL LINEARITY ERROR
fIN = 1MHz
20 40 60 80 1024
Output Code
1.0
0.5
0
–0.5
–1.0
0
DIFFERENTIAL LINEARITY ERROR
fIN = 10MHz
20 40
60 80 1024
Output Code
2.0
1.0
0
–1.0
–2.0
0
INTEGRAL LINEARITY ERROR
256 512 768
Output Code
1024
SWEPT POWER SFDR
100
80
dBFS
60
40
dBc
20
0
–60 –50 –40 –30 –20 –10
Input Amplitude (dBFS)
0
®
ADS822, ADS825
6

6 Page









ADS822E pdf, datenblatt
SNR is given by the following equation. If this value is near
your system requirements, input clock jitter must be reduced.
Jitter SNR = 20 log 1 rms signal to rms noise
2πƒ IN tA
where: ƒIN is input signal frequency
tA is rms clock jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have 50% duty cycle (tH = tL), along with fast rise and fall
times of 2ns or less. The clock input of the ADS825 can be
driven with either 3V or 5V logic levels. Using low-voltage
logic (3V) may lead to improved AC performance of the
converter.
Digital Outputs
The output data format of the ADS822 and ADS825 are in
positive Straight Offset Binary code (see Tables I and II).
This format can easily be converted into the Binary Two’s
Complement code by inverting the MSB.
It is recommended to keep the capacitive loading on the data
lines as low as possible (15pF). Higher capacitive loading
will cause larger dynamic currents as the digital outputs are
changing. Those high current surges can feed back to the
analog portion of the ADS822 and ADS825 and affect the
performance. If necessary, external buffers or latches close
to the converter’s output pins may be used to minimize the
capacitive loading. They also provide the added benefit of
isolating the ADS822 and ADS825 from any digital noise
activities on the bus coupling back high frequency noise.
SINGLE-ENDED INPUT
(IN = CMV)
+FS –1LSB (IN = REFT)
+1/2 Full Scale
Bipolar Zero (IN = CMV)
–1/2 Full Scale
–FS (IN = REFB)
STRAIGHT OFFSET BINARY
(SOB)
11 1111 1111
11 0000 0000
10 0000 0000
01 0000 0000
00 0000 0000
TABLE I. Coding Table for Single-Ended Input Configura-
tion with IN Tied to the Common-Mode Voltage
(CMV).
DIFFERENTIAL INPUT
+FS –1LSB (IN = +3V, IN = +2V)
+1/2 Full Scale
Bipolar Zero (IN = IN = CMV)
–1/2 Full Scale
–FS (IN = +2V, IN = +3V)
STRAIGHT OFFSET BINARY
(SOB)
11 1111 1111
11 0000 0000
10 0000 0000
01 0000 0000
00 0000 0000
TABLE II. Coding Table for Differential Input Configuration
and 2Vp-p Full-Scale Range.
Digital Output Driver (VDRV)
The ADS822 features a dedicated supply pin for the output
logic drivers, VDRV, which is not internally connected to
the other supply pins. Setting the voltage at VDRV to +5V
or +3V, the ADS822 and ADS825 produce corresponding
logic levels and can directly interface to the selected logic
family. The output stages are designed to supply sufficient
current to drive a variety of logic families. However, it is
recommended to use the ADS822 and ADS825 with +3V
logic supply. This will lower the power dissipation in the
output stages due to the lower output swing and reduce
current glitches on the supply line which may affect the AC-
performance of the converter. In some applications, it might
be advantageous to decouple the VDRV pin with additional
capacitors or a pi-filter.
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multilayer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. The ADS822 and ADS825
should be treated as analog components. Whenever possible,
the supply pins should be powered by the analog supply.
This will ensure the most consistent results since digital
supply lines often carry high levels of noise which otherwise
would be coupled into the converter and degrade the achiev-
able performance. All ground connections on the ADS822
and ADS825 are internally joined together obviating the
design of split ground planes. The ground pins (1, 16, 26)
should directly connect to an analog ground plane which
covers the PC board area around the converter. While
designing the layout, it is important to keep the analog signal
traces separated from any digital lines to prevent noise
coupling onto the analog signal path. Due to their high
sampling rates, the ADS822 and ADS825 generate high
frequency current transients, and noise (clock feedthrough)
that are fed back into the supply and reference lines. This
requires that all supply and reference pins are sufficiently
bypassed. Figure 9 shows the recommended decoupling
scheme for the ADS822 and ADS825. In most cases, 0.1µF
ceramic chip capacitors at each pin are adequate to keep the
impedance low over a wide frequency range. Their effec-
tiveness largely depends on the proximity to the individual
supply pin. Therefore, they should be located as close to the
supply pins as possible. In addition, a larger bipolar capaci-
tor (1µF to 22µF) should be placed on the PC board in
proximity of the converter circuit.
ADS822
ADS825
+VS
GND
+VS
GND VDRV
27
26 15
16 28
0.1µF
0.1µF 0.1µF
10µF
+
®
ADS822, ADS825
+5V +3/+5V
Figure 9. Recommended Bypassing for the Supply Pins.
12

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