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ADS821 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS821
Beschreibung 10-Bit/ 40MHz Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 15 Seiten
ADS821 Datasheet, Funktion
®
ADS821U
ADS821E
ADS821
TM 10-Bit, 40MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q NO MISSING CODES
q INTERNAL REFERENCE
q LOW POWER: 380mW
q HIGH SNR: 58dB
q INTERNAL TRACK/HOLD
q PACKAGE: 28-Pin SOIC and SSOP
APPLICATIONS
q VIDEO DIGITIZING
q ULTRASOUND IMAGING
q GAMMA CAMERAS
q SET-TOP BOXES
q CABLE MODEMS
q CCD IMAGING
Color Copiers
Scanners
Camcorders
Security Cameras
Fax Machines
q IF AND BASEBAND DIGITIZATION
q TEST INSTRUMENTATION
IN
IN
REFT
CM
REFB
DESCRIPTION
The ADS821 is a low power, monolithic 10-bit, 40MHz
analog-to-digital converter utilizing a small geometry
CMOS process. This COMPLETE converter includes
a 10-bit quantizer with internal track/hold, reference,
and a power down feature. It operates from a single
+5V power supply and can be configured to accept
either differential or single-ended input signals.
The ADS821 employs digital error correction to pro-
vide excellent Nyquist differential linearity perfor-
mance for demanding imaging applications. Its low
distortion, high SNR and high oversampling capability
give it the extra margin needed for telecommunications
and video applications.
This high performance converter is specified for AC
and DC performance at a 40MHz sampling rate. The
ADS821 is available in 28-pin SOIC and SSOP
packages.
CLK
MSBI
OE
Timing
Circuitry
T/H
+3.25V
Pipeline
A/D
Error
Correction
Logic
3-State
Outputs
10-Bit
Digital
Data
+1.25V
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1995 Burr-Brown Corporation
PDS-1291D
Printed in U.S.A. November, 1996






ADS821 Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = +5V, Sampling Rate = 40MHz, with a 50% duty cycle clock having a 2ns rise/fall time, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
0.0
TWO-TONE INTERMODULATION
f1 = 4.47MHz
f2 = 4.39MHz
5.00
10.00
Frequency (MHz)
15.00
20.00
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
70
SFDR
65
60
55
0.1
SNR
1 10
Frequency (MHz)
100
SWEPT POWER SFDR
100
fIN = 12MHz
80
60
40
20
0
–50 –40 –30 –20 –10
Input Amplitude (dBm)
0
10
SWEPT POWER SNR
60
fIN = 12MHz
50
40
30
20
10
0
–50 –40 –30 –20 –10
Input Amplitude (dBm)
0
10
INTEGRAL LINEARITY ERROR
4.0
fIN = 500kHz
2.0
0
–2.0
–4.0
0.0
0.20
0.40
0.60
Code
0.80
1.0
DYNAMIC PERFORMANCE
vs SINGLE-ENDED FULL-SCALE INPUT RANGE
65
SFDR (fIN = 12MHz)
60
SNR (fIN = 12MHz)
55
SFDR (fIN = 500kHz)
50 SNR (fIN = 500kHz)
45
40
234
Single-Ended Full-Scale Input Range (Vp-p)
NOTE: REFTEXT varied, REFB is fixed at the internal value of +1.25V.
®
ADS821
6

6 Page









ADS821 pdf, datenblatt
The total load of the resistor string should be selected so that
the current does not exceed 1mA. Although the circuit in
Figure 7 uses two resistors of equal value so that the common
mode voltage is centered between the top and bottom refer-
ence (+2.25V), it is not necessary to do so. In all cases the
center point, VCM, should be bypassed to ground in order to
provide a low impedance AC ground.
If the signal needs to be DC coupled to the input of the
ADS821, an operational amplifier input circuit is required.
In the differential input mode, any single-ended signal must
be modified to create a differential signal. This can be
accomplished by using two operational amplifiers, one in
the noninverting mode for the input and the other amplifier
in the inverting mode for the complementary input. The low
distortion circuit in Figure 8 will provide the necessary input
shifting required for signals centered around ground. It also
employs a diode for output level shifting to guarantee a low
distortion +3.25V output swing. Another DC-coupled circuit
is shown in Figure 9. Other amplifiers can be used in place
of the OPA642s if the lowest distortion is not necessary. If
output level shifting circuits are not used, care must be taken
to select operational amplifiers that give the necessary per-
formance when swinging to +3.25V with a ±5V supply
operational amplifier. The OPA620 and OPA621, or the
lower power OPA650 or OPA651 can be used in place of the
OPA642s in Figure 8. In that configuration, the OPA650 and
OPA651 will typically swing to within 100mV of positive
full scale. If the OPA621 or OPA651 is used, the input
buffer must be configured in a gain of 2.
The ADS821 can also be configured with a single-ended
input full scale range of +0.25V to +4.25V by tying the
complementary input to the common-mode reference voltage
as shown in Figure 10. This configuration will result in
increased even-order harmonics, especially at higher input
frequencies. However, this tradeoff may be quite acceptable
for time-domain applications. The driving amplifier must
give adequate performance with a +0.25V to +4.25V output
swing in this case.
EXTERNAL REFERENCES AND ADJUSTMENT OF
FULL SCALE RANGE
The internal reference buffers are limited to approximately
1mA of output current. As a result, these internal +1.25V
and +3.25V references may be overridden by external refer-
ences that have at least 18mA (at room temperature) of
output drive capability. In this instance, the common-mode
voltage will be set halfway between the two references. This
feature can be used to adjust the gain error, improve gain
drift, or to change the full scale input range of the ADS821.
Changing the full scale range to a lower value has the benefit
of easing the swing requirements of external input amplifi-
ers. The external references can vary as long as the value of
the external top reference (REFTEXT) is less than or equal to
+3.4V and the value of the external bottom reference
(REFBEXT) is greater than or equal to +1.1V and the differ-
ence between the external references are greater than or
equal to 800mV.
For the differential configuration, the full scale input range
will be set to the external reference values that are selected.
For the single-ended mode, the input range is 2•(REFTEXT
REFBEXT), with the common-mode being centered at
(REFTEXT + REFBEXT)/2. Refer to the typical performance
curves for expected performance vs full scale input range.
The circuit in Figure 11 works completely on a single +5V
supply. As a reference element, it uses the micro-power
reference REF1004-2.5, which is set to a quiescent current
of 0.1mA. Amplifier A2 is configured as a follower to buffer
the +1.25V generated from the resistor divider. To provide
the necessary current drive, a pull-down resistor, RP is
added.
Amplifier A1 is configured as an adjustable gain stage, with
a range of approximately 1 to 1.32. The pull-up resistor
again relieves the op amp from providing the full current
drive. The value of the pull-up/down resistors is not critical
and can be varied to optimize power consumption. The need
for pull-up/down resistors depends only on the drive capa-
bility of the selected drive amplifier and thus can be omitted.
CIN
0.1µF
RIN1
25
RIN2
25
CIN
0.1µF
*RSER1
49.9
R3
1k
C2
0.1µF
*RSER2
49.9
NOTE: * indicates optional component.
FIGURE 7. AC-Coupled Differential Input Circuit.
®
ADS821
R1
(6kΩ)
CSH1
22pF
VCM
C1
0.1µF
IN
R2
(6kΩ)
CSH2
22pF
IN
C3
0.1µF
12
+3.25V
Top Reference
ADS8xx
+1.25V
Bottom Reference

12 Page





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