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PDF ADS808 Data sheet ( Hoja de datos )
| Número de pieza | ADS808 | |
| Descripción | 12-Bit/ 70MHz Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS808 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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ADS808
ADS808
SBAS179C – DECEMBER 2000 – REVISED SEPTEMBER 2002
12-Bit, 70MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q DYNAMIC RANGE:
SNR: 64dB at 10MHz fIN
SFDR: 68dB at 10MHz fIN
q PREMIUM TRACK-AND-HOLD:
Low Jitter: 0.25ps rms
Differential or Single-Ended Inputs
Selectable Full-Scale Input Range
q FLEXIBLE CLOCKING:
Differential or Single-Ended
Accepts Sine or Square Wave Clocking
Down to 0.5Vp-p
Variable Threshold Level
APPLICATIONS
q BASESTATION WIDEBAND RADIOS:
CDMA, GSM, TDMA, 3G, AMPS, and NMT
q TEST INSTRUMENTATION
q CCD IMAGING
DESCRIPTION
The ADS808 is a high-dynamic range, 12-bit, 70MHz,
pipelined Analog-to-Digital Converter (ADC). It includes a
high-bandwidth linear track-and-hold that has a low jitter of
only 0.25ps rms, leading to excellent SNR performance. The
clock input can accept a low-level differential sine wave or
square wave signal down to 0.5Vp-p, further improving the
SNR performance. It also accepts a single-ended clock
signal and has flexible threshold levels.
The ADS808 has a 2Vp-p differential input range (1Vp-p • 2
inputs) for optimum signal-to-noise ratio. The differential
operation gives the lowest even-order harmonic compo-
nents. A lower input voltage of 1.5Vp-p or 1Vp-p can also be
selected using the internal references, further optimizing
SFDR. Alternatively, a single-ended input range can be used
by tying the IN input to the common-mode voltage, if desired.
The ADS808 also provides an over-range flag that indicates
when the input signal has exceeded the converter’s full-scale
range. This flag can also be used to reduce the gain of the
front-end signal conditioning circuitry. It also employs digital
error-correction techniques to provide excellent differential
linearity for demanding imaging applications. The ADS808 is
available in a small TQFP-48 PowerPAD™ thermally en-
hanced package.
PowerPAD is a registered trademark of Texas Instruments.
1Vp-p
1Vp-p
IN
IN
ADS808
T&H
+VS DV
Timing Circuitry
CLK
CLK
12-Bit
Pipelined
ADC Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D11
CM
(+2.5V)
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
VREF SEL1 SEL2 REFB
OE VDRV
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2000, Texas Instruments Incorporated
1 page  
TIMING DIAGRAM
Analog In
Clock
Data Bits Out
Data Valid Pulse
N+6
N
N+1
N+3
N+4
N+5
tA
tCONV
N+2
tH tL
N+7
N–5
5 Clock Cycles
N–4
N–3
N–2
t1
N–1
t2
tDV
N
N+1
SYMBOL
DESCRIPTION
MIN(1)
TYP
MAX(1) UNITS
t CONV
tH
tL
tA
tDV
t1
t2
Convert Clock Period
Clock Pulse HIGH
Clock Pulse LOW
Aperture Delay
Data Valid Pulse Delay(2)
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
14.3
7
7
4
t CONV / 2
t CONV / 2
4.6
11.5
5
9
1µs
6.1
14
11
ns
ns
ns
ns
ns
ns
ns
NOTES: (1) Timing values based on simulation at room temperature. Min/Max values provided for
design estimation only. (2) Measured from the 50% point of the clock to the time when signals are
within valid logic levels.
REFERENCE AND FULL-SCALE RANGE SELECT
DESIRED
FULL-SCALE RANGE
1Vp-p
1.5Vp-p
2Vp-p
SEL1
VREF
GND
GND
SEL2
GND
+VS
GND
INTERNAL
VREF
0.5V
0.75V
1.0V
NOTE: For external reference operation, tie VREF to +VS and apply REFT and REFB externally. Internal voltage buffer of CM is powered up. The full-scale input range
is equal to 2x the reference value (REFT – REFB).
ADS808
SBAS179C
www.ti.com
5
5 Page 
attenuate some of the wideband noise. The actual compo-
nent values would need to be tuned for the individual appli-
cation requirements. As a guideline, resistor values are
typically in the range of 10Ω to 100Ω, capacitors in the range
of 10pF to 200pF. In any case, the RIN and CIN values should
have a low tolerance. This will ensure that the ADS808 sees
closely matched source impedances.
AC-Coupled, Differential Interface with Gain
The interface circuit example presented in Figure 6 employs
two OPA685s, (current-feedback op amps), optimized for
gains of 8V/V or higher. The input transformer (T1) converts
the single-ended input signal to a differential signal required
at the amplifier’s inverting inputs, that are tuned to provide a
50Ω impedance match to an assumed 50Ω source. To
achieve the 50Ω input match at the primary of the 1:2
transformer, the secondary input must see a 200Ω load
impedance. Both amplifiers are configured for the inverting
mode resulting in close gain and phase matching of the
differential signal. This technique, along with a highly sym-
metrical layout, is instrumental in achieving a substantial
reduction of the 2nd-harmonic, while retaining excellent 3rd-
order performance. A common-mode voltage (VCM) is ap-
plied to the noninverting inputs of the OPA685. Additional
series of 43.2Ω resistors isolate the output of the op amps
from the capacitive load presented by the 22pF capacitors
and the input capacitance of the ADS808. This 43.2Ω/22pF
combination sets a pole at approximately 167MHz and rolls
off some of the wideband noise.
REFERENCE
REFERENCE OPERATION
Integrated into the ADS808 is a bandgap reference circuit
including some logic that provides a +0.5V, +0.75V, or +1V
reference output by selecting the corresponding pin-strap
configuration. Table I gives a complete overview of the
possible reference options and pin configurations.
VCM
50Ω Source
VI
Noise
Figure
11.8dB
T1
1:2
100Ω
100Ω
VCM
+5V
DIS
OPA685
–5V 600Ω
600Ω
+5V
DIS
OPA685
–5V
Power-supply decoupling
not shown.
43.2Ω
43.2Ω
22pF
VO A/D Converter Input
22pF
VO = 12V/V (21.6dB)
VI
FIGURE 6. Wideband Differential A/D Converter Driver.
DESIRED FULL-SCALE RANGE,
FSR (Differential)
CONNECT SEL1 CONNECT SEL2
(Pin 33)
(Pin 32)
VOLTAGE AT VREF
(Pin 34)
VOLTAGE AT REFT
(Pin 41)
2Vp-p (+10dBm)
1.5Vp-p (+7.5dBm)
1Vp-p
External Reference
GND
GND
VREF
—
GND
+VS
GND
—
+1.0V
+0.75V
+0.5V
> +3.5V
+3V
+2.875V
+2.75V
+2.75V to +4.5V
TABLE I. Reference Pin Configurations and Corresponding Voltage on the Reference Pins.
VOLTAGE AT REFB
(Pin 39)
+2V
+2.125V
+2.25V
+0.5V to +2.25V
ADS808
SBAS179C
www.ti.com
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet ADS808.PDF ] | |
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