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PDF ADS807 Data sheet ( Hoja de datos )
| Número de pieza | ADS807 | |
| Descripción | 12-Bit/ 53MHz Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS807 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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®
ADS807E
ADS807
TM 12-Bit, 53MHz Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q SPURIOUS FREE DYNAMIC RANGE:
82dB at 10MHz fIN
q HIGH SNR: 67.5dB (2Vp-p), 69dB (3Vp-p)
q LOW POWER: 335mW
q INTERNAL OR EXTERNAL REFERENCE
q LOW DNL: 0.5LSB
q FLEXIBLE INPUT RANGE: 2Vp-p to 3Vp-p
q 28-LEAD SSOP PACKAGE
APPLICATIONS
q COMMUNICATIONS IF PROCESSING
q COMMUNICATIONS BASESTATIONS
q TEST EQUIPMENT
q MEDICAL IMAGING
q VIDEO DIGITIZING
q CCD DIGITIZING
ADS807
DESCRIPTION
The ADS807 is a high-speed, high dynamic range,
12-bit pipelined analog-to-digital converter. This con-
verter includes a high-bandwidth track-and-hold that
gives excellent spurious performance up to and beyond
the Nyquist rate. The differential nature of this track-
and-hold and A/D circuitry minimizes even-order har-
monics and gives excellent common-mode noise immu-
nity. The track-and-hold can also be operated single-
ended.
The ADS807 provides for setting the full-scale range
of the converter without any external reference cir-
cuitry. The internal reference can be disabled allowing
low drive, internal references to be used for improved
tracking in multichannel systems.
The ADS807 provides an overrange indicator flag to
indicate an input signal that exceeds the full-scale input
range of the converter. This flag can be used to reduce
the gain of front end gain control circuitry. There is
also an output enable pin to allow for multiplexing and
testability on a PC board.
The ADS807 employs digital error correction tech-
niques to provide excellent differential linearity for
demanding imaging applications.
CLK
Timing
Circuitry
+3V
+2.5V
+2V
+3V
+2.5V
+2V
IN
IN
(Opt.)
CM
T/H
Pipelined
A/D
Error
Correction
Logic
3-State
Outputs
D0
•
•
•
D11
Internal
Reference
Optional External
Reference
INT/EXT FSSEL
OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-1396C
Printed in U.S.A. January, 1999
1 page  
TIMING DIAGRAM
Analog In N
N+1 N+2 N+3 N+4 N+5 N+6 N+7
Clock
tD tCONV
tL tH
Data Out
6 Clock Cycles
N–6 N–5 N–4 N–3 N–2 N–1
t2
N
Data Invalid
t1
N+1
SYMBOL
DESCRIPTION
MIN TYP
tCONV
tL
tH
tD
t1 (1)
t2 (1)
Convert Clock Period
Clock Pulse Low
Clock Pulse High
Aperture Delay
Data Hold Time, CL = 0pF
New Data Delay Time, CL = 15pF max
18.87
9.4
9.4
2.7
tCONV/2
tCONV/2
2
NOTE: (1) t1 and t2 times are valid for VDRV voltages of +2.7V to +5V.
MAX
100µs
12
UNITS
ns
ns
ns
ns
ns
ns
®
5 ADS807
5 Page 
402Ω
200Ω
1.82kΩ 1.82kΩ
VIN
16.5Ω 0.1µF
A1
OPA642
REFT
IN
100pF
402Ω
402Ω
ADS807E
A2
OPA642
16.5Ω 0.1µF
1.82kΩ 1.82kΩ
IN
100pF
REFB
FIGURE 2. AC-Coupled Differential Driver Interface with OPA642.
0.1µF
VIN
RIN
249Ω
RF
499Ω
A1
499Ω
+5V
A2
OPA2681
RF
499Ω
RG
249Ω
0.1µF
RS
24.9Ω
RP
499Ω
VCM = +2.5V
RS
24.9Ω
RP
499Ω
68pF
IN
0.1µF
CM
ADS807E
68pF
IN
FIGURE 3. AC-Coupled, Differential Interface for Single-Supply Operation.
AC-Coupled, Single-Ended-to-Differential Interface
for Single-Supply Operation
The previously discussed interface circuit can be modified if
the system only allows for a single supply operation, e.g., VS
= +5V. Single-supply operation requires the driver amplifier
to be biased as well in order to process a bipolar input signal.
Typically, single-supply amplifiers do not achieve distortion
performance as well as dual-supply op amps. The driver
amplifier’s output swing must exceed the full-scale input
range of the converter. In addition, dual op amps, such as the
current-feedback OPA2681, should be considered since they
provide the closest open-loop gain and phase matching
between the two channels. Shown in Figure 3 is a single-
supply interface circuit for an AC-coupled input signal.
With the ADS807 set to the 2Vp-p input range, the top and
bottom references (REFT, REFB) provide an output voltage
of +3.0V and +2.0V, respectively. The CM output of the
ADS807 is used to bias the inputs of the driving amplifiers.
Using the OPA2681 on a single +5V supply, its ideal
common-mode point is +2.5V, which coincides with the
recommended common-mode input level for the ADS807,
thus obviating the need for coupling capacitors between the
amplifiers and the converter.
The addition of a small series resistor (RS) between the
output of the op amps and the input of the ADS807 will be
beneficial in almost all interface configurations. It will
decouple the op amp’s output from the capacitive load and
avoid gain peaking, which can result in increased noise. For
best spurious and distortion performance, the resistor value
should be kept below 100Ω. Furthermore, the series resistor
in combination with the shunt capacitor, establishes a pas-
sive low-pass filter limiting the bandwidth for the wideband
noise thus improving the SNR. The spurious free dynamic
range of this single-supply front end is limited by the 2nd
harmonic distortion. An improvement of several dB may be
realized by adding a pull-down resistor (RP) at the output of
each amplifier. This pulls a DC bias current out of the output
stage of the amplifier. It is set to approximately 5mA in the
shown example, but will vary depending on the amplifier
used.
®
11 ADS807
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ADS807.PDF ] | |
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