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ADS804 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS804
Beschreibung 12-Bit/ 10MHz Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 12 Seiten
ADS804 Datasheet, Funktion
®
ADS804U
ADS804E
ADS804
DEMO BOARD
AVAILABLE
12-Bit, 10MHz Sampling
TM
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q HIGH SFDR: 80dB at NYQUIST
q HIGH SNR: 69dB
q LOW POWER: 180mW
q SMALL 28-LEAD SSOP AND SOIC PACKAGES
q LOW DLE: ±0.3LSB
q FLEXIBLE INPUT RANGE
q OVERRANGE INDICATOR
DESCRIPTION
The ADS804 is a high-speed, high dynamic range, 12-bit pipelined
analog-to-digital converter. This converter includes a high-band-
width track/hold that gives excellent spurious performance up to
and beyond the Nyquist rate. This high-bandwidth, linear track/hold
minimizes harmonics and has low jitter, leading to excellent SNR
performance. The ADS804 is also pin-compatible with the 5MHz
ADS803 and the 20MHz ADS805.
The ADS804 provides an internal reference and can be programmed
for a 2Vp-p input range for the best spurious performance and ease
of driving. Alternatively, the 5Vp-p input range can be used for the
lowest input referred noise of 0.09 LSBs rms giving superior
+VS
ADS804
APPLICATIONS
q IF AND BASEBAND DIGITIZATION
q CCD IMAGING
q SCANNERS
q TEST INSTRUMENTATION
imaging performance. There is also a capability to set the input
range in between the 2Vp-p and 5Vp-p input ranges or to use
external reference. The ADS804 also provides an overrange indica-
tor flag to indicate an input range that exceeds the full-scale input
range of the converter. This flag can be used to reduce the gain of
the front end gain-ranging circuitry.
The ADS804 employs digital error correction techniques to provide
excellent differential linearity for demanding imaging applications.
Its low distortion and high SNR give the extra margin needed for
communications, medical imaging, video and test instrumentation
applications. The ADS804 is available in 28-Lead SSOP and SOIC
packages.
CLK VDRV
Timing Circuitry
VIN IN
T/H
IN
(Opt.)
CM
12-Bit
Pipelined
A/D Core
Error
Correction
Logic
3-State
Outputs
D0
•••
D11
Reference Ladder
and Driver
Reference and
Mode Select
OVR
REFT
VREF
SEL REFB
OE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-1381C
Printed in U.S.A. October, 1998






ADS804 Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = full specified temperature range, VS = +5V, specified single-ended input range = 1.5V to 3.5V, sampling rate = 10MHz, unless otherwise specified.
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
85
80
SFDR
75
70
65 SNR
60
0.1
1
Frequency (MHz)
10
DYNAMIC PERFORMANCE vs INPUT FREQUENCY
(Differential Input, VIN = 5Vp-p)
85
80 SFDR
75
70
SNR
65
60
0.1
1
Frequency (MHz)
10
DIFFERENTIAL LINEARITY vs TEMPERATURE
0.40
fIN = 4.8MHz
0.35
0.30
fIN = 500kHz
0.25
–50
–25
0 25 50
Temperature (°C)
75 100
SPURIOUS FREE DYNAMIC RANGE
vs TEMPERATURE
84
82
fIN = 500kHz
80
fIN = 4.8MHz
78
76
–50
–25
0 25 50
Temperature (°C)
75 100
SIGNAL-TO-NOISE RATIO vs TEMPERATURE
72
fIN = 500kHz
70
68
fIN = 4.8MHz
66
64
–50
–25
0 25 50
Temperature (°C)
75 100
SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
70
69
fIN = 500kHz
68
67
–50
–25
fIN = 4.8MHz
0 25 50
Temperature (°C)
75 100
®
ADS804
6

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ADS804 pdf, datenblatt
necessary, external buffers or latches may be used which
provide the added benefit of isolating the ADS804 from any
MSB digital noise activities on the bus coupling back high fre-
Over = H
quency noise. In addition, resistors in series with each data
line may help maintain the ac performance of the ADS804.
OVR Their use depends on the capacitive loading seen by the
converter. Values in the range of 100to 200will limit
the instantaneous current the output stage has to provide for
Under = H
recharging the parasitic capacitances, as the output levels
change from L to H or H to L.
FIGURE 11. External Logic for Decoding Under- and
Overrange Condition.
CLOCK INPUT REQUIREMENTS
Clock jitter is critical to the SNR performance of high speed,
high resolution analog-to-digital converters. It leads to aper-
ture jitter (tA) which adds noise to the signal being con-
verted. The ADS804 samples the input signal on the rising
edge of the CLK input. Therefore, this edge should have the
lowest possible jitter. The jitter noise contribution to total
SNR is given by the following equation. If this value is near
your system requirements, input clock jitter must be re-
duced.
JitterSNR = 20 log 1 rms signal to rms noise
2πƒ IN tA
Where: ƒIN is Input Signal Frequency
tA is rms Clock Jitter
Particularly in undersampling applications, special consider-
ation should be given to clock jitter. The clock input should
be treated as an analog input in order to achieve the highest
level of performance. Any overshoot or undershoot of the
clock signal may cause degradation of the performance.
When digitizing at high sampling rates, the clock should
have a 50% duty cycle (tH = tL), along with fast rise and fall
times of 2ns or less.
DIGITAL OUTPUTS
The digital outputs of the ADS804 are designed to be
compatible with both high speed TTL and CMOS logic
families. The driver stage for the digital outputs is supplied
through a separate supply pin, VDRV, which is not con-
nected to the analog supply pins. By adjusting the voltage on
VDRV, the digital output levels will vary respectively.
Therefore, it is possible to operate the ADS804 on a +5V
analog supply while interfacing the digital outputs to 3V
logic.
It is recommended to keep the capacitive loading on the data
lines as low as possible (15pF). Larger capacitive loads
demand higher charging currents as the outputs are chang-
ing. Those high current surges can feed back to the analog
portion of the ADS804 and influence the performance. If
GROUNDING AND DECOUPLING
Proper grounding and bypassing, short lead length, and the
use of ground planes are particularly important for high
frequency designs. Multi-layer PC boards are recommended
for best performance since they offer distinct advantages
like minimizing ground impedance, separation of signal
layers by ground layers, etc. It is recommended that the
analog and digital ground pins of the ADS804 be joined
together at the IC and be connected only to the analog
ground of the system.
The ADS804 has analog and digital supply pins, however,
the converter should be treated as an analog component and
all supply pins should be powered by the analog supply. This
will ensure the most consistent results, since digital supply
lines often carry high levels of noise that would otherwise be
coupled into the converter and degrade the achievable per-
formance.
Because of the pipeline architecture, the converter also
generates high frequency current transients and noise that
are fed back into the supply and reference lines. This
requires that the supply and reference pins be sufficiently
bypassed. Figure 12 shows the recommended decoupling
scheme for the analog supplies. In most cases, 0.1µF ce-
ramic chip capacitors are adequate to keep the impedance
low over a wide frequency range. Their effectiveness largely
depends on the proximity to the individual supply pin.
Therefore, they should be located as close to the supply pins
as possible. In addition, a larger size bipolar capacitor (1µF
to 22µF) should be placed on the PC board in close proxim-
ity to the converter circuit.
ADS804
+VS
GND
+VS
GND VDRV
27
26 16
17 28
0.1µF
0.1µF 0.1µF
2.2µF
+
+5V
+5V/+3V
FIGURE 12. Recommended Bypassing for Analog Supply
Pins.
®
ADS804
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