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ADS7870EA Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7870EA
Beschreibung 12-Bit ADC/ MUX/ PGA and Internal Reference DATA ACQUISITION SYSTEM
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 27 Seiten
ADS7870EA Datasheet, Funktion
®
ADS7870
ADS7870
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit ADC, MUX, PGA and Internal Reference
DATA ACQUISITION SYSTEM
FEATURES
q 16-BIT DYNAMIC RANGE
q PGA GAINS: 1, 2, 4, 5, 8, 10, 16, 20V/V
q 4-CHANNEL DIFFERENTIAL/8-CHANNEL
SINGLE ENDED MULTIPLEXER
q 2.048V OR 2.5V INTERNAL REFERENCE
q FAST SERIAL INTERFACE
q HIGH THROUGHPUT RATE: 52ksamples/s
q ERROR/OVERLOAD INDICATOR
q 2.7V TO 5.5V SINGLE-SUPPLY OPERATION
q 4-BIT DIGITAL I/O VIA SERIAL INTERFACE
q SSOP-28 PACKAGE
DESCRIPTION
The ADS7870(1) is a complete low-power data acquisi-
tion system on a single chip. It consists of a 4-channel
differential/8-channel single-ended multiplexer, preci-
sion programmable gain amplifier, 12-bit successive
approximation analog-to-digital converter and a preci-
sion voltage reference.
The programmable-gain amplifier provides high input
impedance, excellent gain accuracy, good common-
mode rejection, and low noise.
For many low-level signals, no external amplification or
impedance buffering is needed between the signal
source and the A/D input.
APPLICATIONS
q PORTABLE/BATTERY POWERED
SYSTEMS
q LOW POWER INSTRUMENTATION
q LOW POWER CONTROL SYSTEMS
q SMART SENSOR APPLICATIONS
The offset voltage of the PGA is auto zeroed. Gains of
1, 2, 4, 5, 8, 10, 16 and 20V/V provide 16-bit dynamic
range and allow signals as low as 125mV to produce full
scale digital outputs.
The ADS7870 contains an internal reference, which is
trimmed for high initial accuracy and stability vs tem-
perature. Drift is typically 10ppm/°C. An external refer-
ence can be used in situations where multiple ADS7870s
share a common reference.
The serial interface allows the use of SPI™, QSPI™,
Microwire™, and 8051-family protocols, without glue
logic.
NOTE: (1) Patent Pending.
VREF BUFIN BUFOUT/REFIN
ADS7870
Analog
Inputs
8 Ch
(4 Ch Diff.)
MUX
I/O 0
I/O 1
I/O 2
I/O 3
Digital
I/O
REF
PGA
BUF Clock
Divider
Oscillator
12-Bit
A/D
Registers
and
Control
Serial
Interface
CCLK
OSC ENABLE
BUSY
CONVERT
RESET
RISE/FALL
CS
SCLK
DIN
DOUT
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1999 Burr-Brown Corporation
PDS-11539A
PArintDedSin 7U.8S.A7.0December, 1999
®






ADS7870EA Datasheet, Funktion
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +5.0V, VREF = 2.5V connected to BUFIN (using internal reference), 2.5MHz CCLK and 2.5MHz SCLK, unless otherwise noted.
GAIN ERROR vs TEMPERATURE
15
10
5
0
–5
–10
–60 –40 –20
Gain= 1
Gain = 8
Gain = 20
0 20 40 60 80 100 120 140
Temperature (°C)
OUTPUT OFFSET ERROR vs TEMPERATURE
10
Gain= 1
8 Gain = 8
Gain = 20
6
4
3
0
–2
–4
–60 –40 –20
0 20 40 60 80 100 120 140
Temperature (°C)
INTERNAL OSCILLATOR FREQUENCY
2.55
vs TEMPERATURE
2.50
2.45
2.40
2.35
2.30
2.25
2.20
–60 –40 –20
+3 Sigma
Avg
–3 Sigma
0 20 40 60 80 100 120 140
Temperature (°C)
OUTPUT OFFSET ERROR
vs COMMON-MODE VOLTAGE
2
1.5
1
0.5
0
–0.5
–1 1 LSB =
–72dB for Gain = 1
–1.5 –98dB for Gain = 20
–2
0 0.5 1 1.5 2 2.5 3 3.5
Common-Mode Voltage (V)
Gain= 1
Gain = 10
Gain = 20
4 4.5 5
VOLTAGE REFERENCE ERROR
vs TEMPERATURE
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
–60
VREF = 2.048V
or 2.5V
–40 –20 0 20 40 60
Temperature (°C)
+3 Sigma
VREF
–3 Sigma
00 100 120
140
8
7
6
5
4
3
2
1
0
–1
2
OUTPUT OFFSET ERROR
vs POWER SUPPLY VOLTAGE
50kS/s, CCLK = 2.5MHz,
VREF = 2.048V
4 LSB =
86dB (Gain = 20)
60dB (Gain = 1)
Gain= 1
Gain = 10
Gain = 20
2.5 3 3.5 4 4.5 5 5.5 6
VDD (V)
®
ADS7870
6

6 Page









ADS7870EA pdf, datenblatt
The structure of the instruction byte for direct mode is
shown in Table I.
• D7: This bit is set to “1” for direct mode operation
• D6 through D4 (G2-G0): These bits control the gain of the
programmable gain amplifier. PGA gains of 1, 2, 4, 5, 8, 10,
16 and 20 are available. The coding is shown in Table I.
• D3 through D0 (M3-M0): These bits configure the switches
that determine the input channel selection. The input
channels may be placed in either differential or single
ended configurations. In the case of differential configu-
ration, the polarity of the input signal is reversible. The
coding is shown in Table III.
Note that the seven lower bits of this byte are written to
register 4, the Gain/Mux register.
All other controllable ADS7870 parameters are values pre-
viously stored in their respective registers. These values are
either the power-up default values or values that were
previously written to one of the control registers in an
Register mode operation. No additional data is required for
a direct mode instruction.
Register Mode
In register mode (Bit D7 of the Instruction Byte is “0”) a
read or write instruction to one of the ADS7870’s registers
is initiated. All of the user determinable functions and
features of the ADS7870 can be controlled by writing
information to these registers (see Table II). Conversion
results can be read from the A/D Output registers.
The Instruction Byte (see Table I) contains the address of the
register for the next read/write operation, determines whether
the serial communication is to be done in 8-bit or 16-bit
word length, and determines whether next operation will
read-from or write-to the addressed register.
The structure of the instruction byte for register mode is
shown in Table I.
• D7: This bit is set to “0” for “register” mode operation.
• D6 (R/W): Bit 6 of the Instruction Byte determines whether
a read or write operation is performed, “1” for a read or
“0” for a write.
• D5 (16/8): This bit determines the word length of the read
or write operation that follows, “1” for sixteen bits (two
eight-bit bytes) or “0” for eight bits.
• D4 through D0 (AS4-AS0): These bits determine the
address of the register that is to be read-from or written-
to. See Table II for register address coding and other
information.
For sixteen-bit operations, the first eight bits will be written-
to/read-from the address encoded by instruction byte, bits
AS4 through AS0 (Register Address). The address of the
next eight bits depends on whether the Register Address for
the first byte is odd or even. If it is even, then the address for
the second byte will be Register Address + 1. If the Register
Address is odd, then the address for the second byte is the
Register Address – 1.
This arrangement allows transfer of conversion results from
the two A/D Output Data registers either MS byte first or LS
byte first (see Serial Interface Control Register text).
Register Summary
A summary of information about the ADS7870 addressable
registers is shown in Table II. Brief descriptions of the ten
user-addressable registers follow. More detailed information
on the individual registers is provided in the INTERNAL
USER-ACCESSIBLE REGISTERS section.
Registers 0 and 1, the A/D output data registers, contain the
least significant and most significant bits (ADC0 through
ADC11) of the A/D conversion result. Register 0 also
contains a bit that indicates if the allowable internal voltage
limits for the PGA have been exceeded (OVR).
Register 2, the PGA Valid Register, contains information
that describes the nature of the problem in the event that the
allowable input voltage to the PGA has been exceeded.
Register 3, the A/D Control Register, contains information
regarding the serial interface; a frequency division factor
used for the conversion clock function (CDF0 and CDF1)
and configuration control of an automatic read back option
(RBM0 and RBM1).
Register 4, the Gain/Mux Register, contains the input chan-
nel selection information (M0 through M3) and the pro-
grammable gain amplifier gain set bits (G0 through G2).
Register 5, the Digital I/O State Register, contains the state
of each of the digital I/O pins (I/O3 through I/O0).
REGISTER ADDRESS
AS4 AS3 AS2 AS1 AS0
0 0 00 0
0 0 00 1
0 0 01 0
0 0 01 1
0 0 10 0
0 0 10 1
0 0 11 0
0 0 11 1
1 1 00 0
1 1 11 1
ADDR
N0.
0
1
2
3
4
5
6
7
24
31
READ/
WRITE
Read
Read
Read
R/W
R/W
R/W
R/W
R/W
R/W
Read
D7(MSB)
ADC3
ADC11
0
0
CNV/BSY
CNV/BSY
0
0
LSB
0
D6
ADC2
ADC10
0
0
G2
0
0
0
2W/3
0
TABLE II. Register Address Map.
REGISTER ADDRESS
D5 D4 D3 D2
ADC1
ADC9
VLD5
0
G1
0
0
OSCR
8051
0
ADC0
ADC8
VLD4
0
G0
0
0
OSCE
0
0
0
ADC7
VLD3
RBM1
M3
IO3
OE3
REFE
0
0
0
ADC6
VLD2
RBM0
M2
IO2
OE2
BUFE
8501
0
D1
0
ADC5
VLD1
CFD1
M1
IO1
OE1
R2V
2W/3
0
D0
OVR
ADC4
VLD0
CFD0
M0
IO0
OE0
RGB
LSB
1
REGISTER
NAME
A/D Output Data, LS Byte
A/D Output Data, MS Byte
PGA Valid Register
A/D Control Register
Gain/Mux Register
Digital I/O State Register
Digital I/O Control Register
Ref/Oscillator Control Register
Serial Interface Control
ID Register
®
ADS7870
12

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