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ADS7864YB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7864YB
Beschreibung 500kHz/ 12-Bit/ 6-Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 16 Seiten
ADS7864YB Datasheet, Funktion
ADS7864
ADS7864
SBAS141
500kHz, 12-Bit, 6-Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 6 SIMULTANEOUS SAMPLING CHANNELS
q FULLY DIFFERENTIAL INPUTS
q 2µs TOTAL THROUGHPUT PER CHANNEL
q GUARANTEED NO MISSING CODES
q PARALLEL INTERFACE
q 1MHz EFFECTIVE SAMPLING RATE
q LOW POWER: 50mW
q 6X FIFO
APPLICATIONS
q MOTOR CONTROL
q MULTI-AXIS POSITIONING SYSTEMS
q 3-PHASE POWER CONTROL
DESCRIPTION
The ADS7864 is a dual 12-bit, 500kHz Analog-to-
Digital (A/D) converter with 6 fully differential input
channels grouped into three pairs for high speed simul-
taneous signal acquisition. Inputs to the sample-and-
hold amplifiers are fully differential and are main-
tained differential to the input of the A/D converter.
This provides excellent common-mode rejection of
80dB at 50kHz which is important in high noise
environments.
The ADS7864 offers a parallel interface and control
inputs to minimize software overhead. The output data
for each channel is available as a 16-bit word (address
and data). The ADS7864 is offered in a TQFP-48
package and is fully specified over the –40°C to +85°C
operating range.
HOLDA
CH A0+
CH A0–
HOLDB
CH B0+
CH B0–
HOLDC
CH C1+
CH C1–
REFIN
REFOUT
CH A1+
CH A1–
CH B1+
CH B1–
CH C1+
CH C1–
S/H
Amp
S/H
Amp
S/H
Amp
MUX
S/H
Amp
S/H
Amp
S/H
Amp
MUX
SAR
CDAC
COMP
Internal
2.5V
Reference
CDAC
COMP
SAR
Interface
A2
A1
Conversion
and
Control
A0
BYTE
CLOCK
CS
RD
BUSY
RESET
FIFO
Registers
Channel/
16 Data Output
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
http://www.burr-brown.com/
http://www.ti.com/
Copyright © 2000, Texas Instruments Incorporated
PDS-11581A
ADS7864Printed in U.S.A. September, 2000
®






ADS7864YB Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
1.50
NEGATIVE GAIN MATCH vs TEMPERATURE
(Maximum Deviation for All Six Channels)
1.40
1.30
1.20
1.10
1.00
–40
–20
0 20 40
Temperature (°C)
60
80
2.510
REFERENCE VOLTAGE vs TEMPERATURE
2.506
2.502
2.498
2.494
2.490
–40
–20
0 20 40
Temperature (°C)
60
80
BIPOLAR ZERO vs TEMPERATURE
1.2
1.0
0.8
CH1
0.6
CH0
0.4
–40
–20
0 20 40
Temperature (°C)
60
80
1.30
BIPOLAR ZERO MATCH vs TEMPERATURE
1.20
1.10
1.00
0.90
–40
–20
0 20 40
Temperature (°C)
60
80
1
0.75
DIFFERENTIAL LINEARITY ERROR vs CODE
Typical of All Six Channels
0.5
0.25
0
–0.25
–0.5
–0.75
–1
800
000
Hex BTC Code
7FF
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
800
INTEGRAL LINEARITY ERROR vs CODE
Typical of All Six Channels
000
Hex BTC Code
7FF
®
ADS7864
6

6 Page









ADS7864YB pdf, datenblatt
time, the falling edge of HOLDB takes place just before the
falling edge of clock. One conversion requires 16 clock
cycles. Here, data is read after the next conversion is initi-
ated by HOLDB. To read data from channel B, A1 is set
high and A2 is low. As A0 is low during the first reading (A2
A1 A0 = 010) data B0 is put to the output. Before the second
RD, A0 switches high (A2 A1 A0 = 011) so data from
channel B1 is read.
READING DATA (RD, CS)—In general, the channel/data
outputs are in tristate. Both, CS and RD have to be LOW to
enable these outputs. RD and CS have to stay LOW together
for at least 30ns (Figure 10, t13) before the output data is
valid. RD has to remain high for at least 30ns (Figure 10, t14)
before bringing it back LOW for a subsequent read com-
mand.
12.5 clock-cycles after the start of a conversion (BUSY
going LOW), the new data is latched into its output register.
If a read process is initiated around 12.5 clock cycles after
BUSY went LOW, RD and CS should stay LOW for at least
50ns to get the new data stored to its register and switched
to the output.
CS being LOW tells the ADS7864 that the bus on the board
is assigned to the ADS7864. If an A/D converter shares a bus
with digital gates, there is a possibility, that digital (high
frequency) noise gets coupled into the A/D converter. If the
bus is just used by the ADS7864, CS can be hardwired to
ground. Reading data at the falling edge of one of the hold
signals might cause distortion of hold value.
OUTPUT CODE (DB15…DB0)
The ADS7864 has a 16 bit output word. DB15 is 1 if the
output contains valid data. This is important for the FIFO
mode. Valid Data can be read until DB15 switches to 0.
DB14, DB13 and DB12 store channel information as indi-
cated in Table I (Channel Truth Table). The 12 bit output
data is stored from DB11 (MSB) to DB0 (LSB).
DATA CHANNEL
A0
A1
B0
B1
C0
C1
DB14
0
0
0
0
1
1
TABLE I. Channel Truth Table.
DB13
0
0
1
1
0
0
DB12
0
1
0
1
0
1
BYTE—If there is only an 8-bit bus available on a board
then Byte can be set HIGH (see Figures 11 and 12). In this
case, the lower eight bits can be read at the output pins DB7
to DB0 at the first RD signal and the higher bits after the
second RD signal.
GETTING DATA
The ADS7864 has three different output modes that are
selected with A2, A1 and A0.
With (A2 A1 A0) = 000 to 101 a particular channel can
directly be addressed (see Table II and Figure 9). The
channel address should be set at least 10ns (Figure 10, t12)
before the falling edge of RD and should not change as long
as RD is low.
CHANNEL SELECTED/
MODE
A0
A1
B0
B1
C0
C1
Cycle Mode
FIFO Mode
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
TABLE II. Address/Mode Truth Table.
A0
0
1
0
1
0
1
0
1
BUSY
CLOCK
HOLDB
CS
RD
A0
FIGURE 10. Timing for Reading Data.
®
ADS7864
t1
t4
t13
t14
t12
12

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