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PDF ADS7862YB Data sheet ( Hoja de datos )
| Número de pieza | ADS7862YB | |
| Descripción | Dual 500kHz/ 12-Bit/ 2 2 Channel Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
ADS7862 ¤
ADS7862
For most current data sheet and other product
information, visit www.burr-brown.com
Dual 500kHz, 12-Bit, 2 + 2 Channel
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 4 INPUT CHANNELS
q FULLY DIFFERENTIAL INPUTS
q 2µs TOTAL THROUGHPUT PER CHANNEL
q GUARANTEED NO MISSING CODES
q PARALLEL INTERFACE
q 1MHz EFFECTIVE SAMPLING RATE
q LOW POWER: 40mW
APPLICATIONS
q MOTOR CONTROL
q MULTI-AXIS POSITIONING SYSTEMS
q 3-PHASE POWER CONTROL
DESCRIPTION
The ADS7862 is a dual 12-bit, 500kHz analog-to-
digital converter (A/D) with 4 fully differential input
channels grouped into two pairs for high speed simulta-
neous signal acquisition. Inputs to the sample-and-hold
amplifiers are fully differential and are maintained dif-
ferential to the input of the A/D converter. This provides
excellent common-mode rejection of 80dB at 50kHz
which is important in high noise environments.
The ADS7862 offers parallel interface and control in-
puts to minimize software overhead. The output data for
each channel is available as a 12-bit word. The ADS7862
is offered in an TQFP-32 package and is full specified
over the –40°C to +85°C operating range.
CH A0+
CH A0–
CH A1+
CH A1–
REFIN
REFOUT
CH B0+
CH B0–
MUX
CH B1+
CH B1–
MUX
S/H
Amp
CDAC
SAR
COMP
Internal
2.5V
Reference
S/H
Amp
CDAC
COMP
SAR
Interface
Conversion
and
Control
A0
CLOCK
CS
RD
BUSY
CONVST
Output
Registers
Data Output
12
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-11475B
ADPrSint7ed8in6U2.S.A. May, 2000
®
1 page  
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VA = +VD = +5V, VREF = internal +2.5V and fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.9kHz, –0.5dB)
62.5
125 187.5
Frequency (kHz)
250
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 199.9kHz, –0.5dB)
62.5
125 187.5
Frequency (kHz)
250
76
74
72
70
68
66
64
1k
SIGNAL-TO-NOISE RATIO AND
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SNR
SINAD
10k 100k
Input Frequency (Hz)
1M
0.25
0.2
0.15
0.1
0.05
0
–0.05
–0.1
–0.15
–0.2
–0.25
–40
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
SINAD
SNR
25
Temperature (°C)
85
0.65
0.45
0.25
0.05
–0.15
–0.35
–0.55
–0.75
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
SFDR
THD
–40 25
Temperature (°C)
85
0.65
0.45
0.25
0.05
–0.15
–0.35
–0.55
–0.75
0.6
0.5
0.4
0.3
0.2
0.1
0
–40
CHANGE IN POSITIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
25 85
Temperature (°C)
150
®
5 ADS7862
5 Page 
mode. Figure 9, in conjunction with Table I, shows the basic
read/write functions of the ADS7862 and highlights all of
the timing specifications. Figure 10 shows a more detailed
description of initiating a conversion using CONVST. Fig-
ure 11 illustrates three consecutive conversions and, with the
accompanying text, describes all of the read and write
capabilities of the ADS7862.
DESCRIPTION
ANALOG INPUT
Full-Scale Input Span
Least Significant
Bit (LSB)
–VREF to +VREF(1)
(–VREF to +VREF)/4096(2)
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
BINARY CODE
HEX CODE
+Full Scale
4.99878V
0111 1111 1111
7FF
Midscale
2.5V
0000 0000 0000
000
Midscale – 1 LSB
2.49878V
1111 1111 1111
FFF
–Full Scale
0V
1000 0000 0000
800
NOTES: (1) –VREF to +VREF around VREF. With a 2.5V reference, this corre-
sponds to a 0V to 5V input span. (2) 1.22mV with a 2.5V reference.
TABLE I. Ideal Input Voltages and Output Codes.
The Figure 11 timing diagram can be divided into three
sections: (a) initiating a conversion (n – 2), (b) starting a
second conversion (n – 1) while reading the data output from
the previous conversion (n – 2), and (c) starting a third
conversion (n) while reading both previous conversions
(n – 2 and n – 1). In this sequence, Channel 0 is converted
first followed by Channel 1. Channel 1 can be converted
prior to Channel 0 if the user wishes by simply starting the
conversion process with the A0 pin at logic HIGH (Channel
1) followed by logic LOW (Channel 0).
TIMING SPECIFICATIONS
SYMBOL
DESCRIPTION
MIN TYP MAX UNITS
tCONV
tACQ
tCKP
tCKL
tCKH
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tF
tR
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
CS to RD Setup Time
CS to RD Hold Time
CONVST LOW
RD Pulse Width
RD to Valid Data (Bus Access)
RD to HI-Z Delay (Bus Relinquish)
Time Between Conversion Reads
Address Setup Time
CONVST HIGH
Address Hold Time
CONVST to BUSY Propagation Delay
CONVST LOW Prior to CLOCK Rising Edge
CONVST LOW After CLOCK Rising Edge
Data Fall Time
Data Rise Time
125
40
40
0
0
15
30
40
250
20
20
10
5
1.75 µs
0.25 µs
5000 ns
ns
ns
ns
ns
ns
ns
16 25 ns
10 20 ns
ns
ns
ns
ns
30 ns
ns
ns
13 25 ns
20 30 ns
CLOCK
CONVST
BUSY
A0
CS
RD
DATA
12
t12 t13
t3
t11
34
tCONV
5
Conversion n
14 15 16
1
2
3
4
5
tACQ
t9
t10
t8
Conversion n + 1
14 15 16
t1 t2
t4
t5
t6
CHA1
CHB1
Conversion n – 1 Results
t7
CHA0
CHB0
Conversion n Results
FIGURE 9. Reading and Writing to the ADS7862 During the Same Cycle.
11
ADS7862
®
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet ADS7862YB.PDF ] | |
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