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PDF ADS7861EB Data sheet ( Hoja de datos )
| Número de pieza | ADS7861EB | |
| Descripción | Dual/ 500kHz/ 12-Bit/ 2 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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®
ADS7861
ADS7861
Dual, 500kHz, 12-Bit, 2 + 2 Channel,
Simultaneous Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 4 INPUT CHANNELS
q FULLY DIFFERENTIAL INPUTS
q 2µs TOTAL THROUGHPUT PER CHANNEL
q GUARANTEED NO MISSING CODES
q 1MHz EFFECTIVE SAMPLING RATE
q LOW POWER: 40mW
q SSI SERIAL INTERFACE
APPLICATIONS
q MOTOR CONTROL
q MULTI-AXIS POSITIONING SYSTEMS
q 3-PHASE POWER CONTROL
DESCRIPTION
The ADS7861 is a dual, 12-bit, 500kHz, analog-to-
digital converter with 4 fully differential input channels
grouped into two pairs for high speed, simultaneous
signal acquisition. Inputs to the sample-and-hold ampli-
fiers are fully differential and are maintained differen-
tial to the input of the A/D converter. This provides
excellent common-mode rejection of 80dB at 50kHz
which is important in high noise environments.
The ADS7861 offers a high speed, dual serial interface
and control inputs to minimize software overhead. The
output data for each channel is available as a 12-bit
word. The ADS7861 is offered in a 24-lead SSOP
package and is fully specified over the –40°C to +85°C
operating range.
CH A0+
CH A0–
CH A1+
CH A1–
REFIN
REFOUT
CH B0+
CH B0–
CH B1+
CH B1–
SHA
CDAC
SAR
COMP
Internal
2.5V
Reference
SHA
CDAC
COMP
SAR
Serial
Interface
SERIAL DATA A
SERIAL DATA B
M0
M1
A0
CLOCK
CS
RD
BUSY
CONVST
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-1508A
Printed in U.S.A. December, 1998
1 page  
TYPICAL PERFORMANCE CURVES
At TA = +25°C, +VA + VD = +5V, and VREF = internal +2.5V, fCLK = 8MHz, fSAMPLE = 500kHz, unless otherwise noted.
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.9kHz, –0.5dB)
62.5
125 187.5
Frequency (kHz)
250
0
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 199.9kHz, –0.5dB)
62.5
125 187.5
Frequency (kHz)
250
76
74
72
70
68
66
64
1k
SIGNAL-TO-NOISE RATIO and
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SNR
SINAD
10k 100k
Input Frequency (Hz)
1M
CHANGE IN SIGNAL-TO-NOISE RATIO
AND SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.7
0.6
0.5
0.4
0.3
0.2
SNR
0.1
SINAD
0
–0.1
–40
25
Temperature (°C)
85
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
AND TOTAL HARMONIC DISTORTION
vs TEMPERATURE
7
6
5
THD
4
3
2
SFDR
1
0
–1
–40
25
Temperature (°C)
85
+1
0
–0.5
–1
–1.5
–2
–2.5
–3
–3.5
0.6
0.5
0.4
0.3
0.2
0.1
0
–40
CHANGE IN POSITIVE GAIN MATCH
vs TEMPERATURE
(Maximum Deviation for All Four Channels)
25 85
Temperature (°C)
150
®
5 ADS7861
5 Page 
HIGH within this window, it is then uncertain as to when the
ADS7861 will initiate conversion (see Figure 8 for a more
detailed description). Sixteen clock cycles are required to
perform a single conversion. Immediately following
CONVST switching to HIGH, the ADS7861 will switch
from the sample mode to the hold mode asynchronous to the
external clock. The BUSY output pin will then go HIGH and
remain HIGH for the duration of the conversion cycle. On
the falling edge of the first cycle of the external clock, the
ADS7861 will latch in the address for the next conversion
cycle depending on the status of the A0 pin (HIGH =
Channel 1, LOW = Channel 0). The address must be selected
15ns prior to the falling edge of cycle one of the external
clock and must remain ‘held’ for 15ns following the clock
edge. For maximum throughput time, the CONVST and RD
pins should be tied together. CS must be brought LOW to
enable the two serial outputs. Data will be valid on the rising
edge of all 16 clock cycles per conversion. The first bit of
data will be a status flag for either Channel 0 or 1, the second
bit will be a second status flag for either Channel A or B.
The subsequent data will be MSB-first through the LSB,
followed by two zeros (see Table II and Figures 9 and 10).
tCKP
125ns
CLOCK
Cycle 1
10ns
CONVST
A
5ns
B
Cycle 2
10ns
5ns
C
NOTE: All CONVST commands which occur more than 10ns before the rising edge of cycle ‘1’ of the external clock
(Region ‘A’) will initiate a conversion on the rising edge of cycle ‘1’. All CONVST commands which occur 5ns after
the rising edge of cycle ‘1’ or 10ns before the rising edge of cycle 2 (Region ‘B’) will initiate a conversion on the
rising edge of cycle ‘2’. All CONVST commands which occur 5ns after the rising edge of cycle ‘2’ (Region ‘C’) will
initiate a conversion on the rising edge of the next clock period. The CONVST pin should never be switched from
LOW to HIGH in the region 10ns prior to the rising edge of the CLOCK and 5ns after the rising edge (gray areas). If
CONVST is toggled in this gray area, the conversion could begin on either the same rising edge of the CLOCK or
the following edge.
FIGURE 8. Conversion Mode.
TIMING SPECIFICATIONS
SYMBOL
DESCRIPTION
MIN
TYP
MAX
tCONV
tACQ
tCKP
tCKL
tCKH
tF
tR
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
Conversion Time
Acquisition Time
Clock Period
Clock LOW
Clock HIGH
DOUT Fall Time
DOUT Rise Time
CONVST HIGH
Address Setup Time
Address Hold Time
RD Setup Time
RD to CS Hold Time
CONVST LOW
RD LOW
CS to Data Valid
CLOCK to Data Valid Delay
Data Valid After CLOCK(1)
1.75
0.25
125
40
40
15
15
15
15
15
20
20
5000
25
30
25
30
1
NOTE: (1) ‘n – 1’ data will remain valid 1ns after rising edge of next CLOCK cycle.
UNITS
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
COMMENTS
When TCKP = 125ns
When TCKP = 125ns
Address latched on falling edge of CLK cycle ‘2’
Before falling edge of CLOCK
After falling edge of CLOCK
Maximum delay following rising edge of CLOCK
Time data is valid after second rising edge of CLOCK
CLOCK CYCLE
1
2 3 4 5 6 7 8 9 10 11 12 13 14
SERIAL DATA CH0 OR CH1 CHA OR CHB DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
15
0
16
0
TABLE II. Serial Data Output Format.
11
ADS7861
®
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet ADS7861EB.PDF ] | |
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| ADS7861EB | Dual/ 500kHz/ 12-Bit/ 2 2 Channel/ Simultaneous Sampling ANALOG-TO-DIGITAL CONVERTER | Burr-Brown Corporation |
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