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ADS7835EB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7835EB
Beschreibung 12-Bit/ High-Speed/ Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 13 Seiten
ADS7835EB Datasheet, Funktion
® ADS7835
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit, High-Speed, Low Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 500kHz THROUGHPUT RATE
q 2.5V INTERNAL REFERENCE
q LOW POWER: 17.5mW
q SINGLE SUPPLY +5V OPERATION
q SERIAL INTERFACE
q GUARANTEED NO MISSING CODES
q MSOP-8
q ±VREF INPUT RANGE
APPLICATIONS
q BATTERY-OPERATED SYSTEMS
q DIGITAL SIGNAL PROCESSING
q HIGH-SPEED DATA ACQUISITION
q WIRELESS COMMUNICATION SYSTEMS
DESCRIPTION
The ADS7835 is a 12-bit, sampling analog-to-digi-
tal converter (A/D) complete with sample-and-hold
(S/H), internal 2.5V reference, and synchronous
serial interface. Typical power dissipation is 17.5mW
at a 500kHz throughput rate. The device can be
placed into a power-down mode which reduces dis-
sipation to just 2.5mW. The input range is –VREF to
+VREF, and the internal reference can be overdriven
by an external voltage.
Low power, small size, and high speed make the
ADS7835 ideal for battery-operated systems such
as wireless communication devices, portable multi-
channel data loggers, and spectrum analyzers. The
serial interface also provides low cost isolation for
remote data acquisition. The ADS7835 is avail-
able in an MSOP-8 package and is guaranteed over
the –40°C to +85°C temperature range.
SAR
CLK
CONV
±2.5V
Input
2k
2k
S/H Amp
CDAC
Comparator
Serial
Interface
DATA
Buffer
Internal
+2.5V Ref
VREF
10k±30%
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-11478B
ADPSrin7ted8i3n U5.S.A.May, 2000
®






ADS7835EB Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, +VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.
75
73
71
69
67
65
63
1
SIGNAL-TO-NOISE and
SIGNAL-TO-(NOISE + DISTORTION)
vs INPUT FREQUENCY
SNR
SINAD
10 100
Input Frequency (kHz)
1000
SPURIOUS FREE DYNAMIC RANGE and
TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
90
85
SFDR
80
75 THDT
70
T First nine harmonics
of the input frequency
65
1 10
100
Input Frequency (kHz)
1000
CHANGE IN SIGNAL-TO-NOISE and
SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.5
0.4 fIN = 10kHz, –0.2dB
0.3
0.2
0.1 SNR
0.0
–0.1
–0.2
SINAD
–0.3
–0.4
–0.5
–40
–20
0
20 40 60 80
Temperature (°C)
100
CHANGE IN SPURIOUS FREE DYNAMIC RANGE
and TOTAL HARMONIC DISTORTION
vs TEMPERATURE
2.0
1.5 fIN = 10kHz, –0.2dB
1.0
0.5 THD
0.0
–0.5
–1.0
–1.5
–2.0
–40
–20
SFDR
First nine harmonics
of the input frequency
0 20 40 60
Temperature (°C)
80 100
1.0
0.8
0.6
0.4
0.2
0.0
–0.2
0
CHANGE IN BIPOLAR OFFSET ERROR
vs SAMPLE RATE
100 200 300 400 500 600 700
Sample Rate (kHz)
®
ADS7835
6

6 Page









ADS7835EB pdf, datenblatt
logic.
DATA FORMAT
The ADS7835 output data is in Binary Two’s Complement
format as shown in Table III. This table shows the ideal
output code for the given input voltage and does not include
DESCRIPTION
Full-Scale Input
Range
Least Significant Bit
(LSB)(2)
+Full Scale
Mid-Scale
Mid-Scale –1LSB
–Full Scale
ANALOG INPUT
–VREF to +VREF(1)
(–VREF to +VREF)/4096
2.49878V
0V
–0.00122V
–2.49878V
DIGITAL OUTPUT
BINARY TWO’S
COMPLEMENT
BINARY
HEX
CODE
CODE
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
NOTES: (1) –2.5V to +2.5V when the internal reference is used. (2) 1.22mV
with a 2.5V reference.
TABLE III. Ideal Input Voltages and Output Codes.
the effects of offset, gain, or noise.
DSP INTERFACING
Figure 7 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
Buffered Serial Port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 8 shows the timing diagram for a typical Serial
Peripheral Interface (SPI) or Queued Serial Peripheral Inter-
face (QSPI). Such interfaces are found on a number of
microcontrollers from various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(Master In Slave Out).
Note the time tDRP shown in Figure 8. This represents the
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the S/H in the hold mode and because the hold
capacitor loses charge over time, there is a requirement that
time tDRP be met as well as the maximum clock period
CONV
CLK 15
16
DATA
12 3
D11
(MSB)
D10
12 13 14
D1
D0
(LSB)
15 16
1 234
D11
(MSB)
D10
D9
FIGURE 7. Typical DSP Interface Timing.
CONV
CLK
DATA
tDRP
123 4
D11
(MSB)
D10
13 14 15
D1
D0
(LSB)
16
FIGURE 8. Typical SPI/QSPI Interface Timing.
®
ADS7835
12
tACQ
1 23
D11
(MSB)

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