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ADS7834PB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7834PB
Beschreibung 12-Bit High Speed Low Power Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 13 Seiten
ADS7834PB Datasheet, Funktion
®
ADS7834
ADS7834
For most current data sheet and other product
information, visit www.burr-brown.com
12-Bit High Speed Low Power Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 500kHz THROUGHPUT RATE
q 2.5V INTERNAL REFERENCE
q LOW POWER: 11mW
q SINGLE SUPPLY +5V OPERATION
q DIFFERENTIAL INPUT
q SERIAL INTERFACE
q GUARANTEED NO MISSING CODES
q MINI-DIP-8 AND MSOP-8
q 0V TO VREF INPUT RANGE
APPLICATIONS
q BATTERY OPERATED SYSTEMS
q DIGITAL SIGNAL PROCESSING
q HIGH SPEED DATA ACQUISITION
q WIRELESS COMMUNICATION SYSTEMS
DESCRIPTION
The ADS7834 is a 12-bit sampling analog-to-digital
converter (A/D) complete with sample/hold, internal
2.5V reference, and synchronous serial interface. Typi-
cal power dissipation is 11mW at a 500kHz through-
put rate. The device can be placed into a power-down
mode which reduces dissipation to just 2.5mW. The
input range is zero to the reference voltage, and the
internal reference can be overdriven by an external
voltage.
Low power, small size, and high-speed make the
ADS7834 ideal for battery operated systems such as
wireless communication devices, portable multi-chan-
nel data loggers, and spectrum analyzers. The serial
interface also provides low-cost isolation for remote
data acquisition. The ADS7834 is available in a plastic
mini-DIP-8 or an MSOP-8 package and is guaranteed
over the –40°C to +85°C temperature range.
SAR
CLK
CONV
+In
–In
S/H Amp
CDAC
Comparator
Serial
Interface
DATA
VREF
Buffer
Internal
+2.5V Ref
10k±30%
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-11457B
ADPrSint7ed8in3U4.S.A. May, 2000
®






ADS7834PB Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (Cont.)
At TA = +25°C, VCC = +5V, fSAMPLE = 500kHz, fCLK = 16 • fSAMPLE, and internal +2.5V reference, unless otherwise specified.
0.00
–20
–40
–60
–80
–100
–120
0
FREQUENCY SPECTRUM
(4096 Point FFT; fIN = 99.7kHz, –0.2dB)
50 100 150 200 250
Frequency (kHz)
76
74
72
70
68
66
64
62
60
1
SIGNAL-TO-NOISE RATIO and
SIGNAL-TO-(NOISE+DISTORTION)
vs INPUT FREQUENCY
SNR
SINAD
10 100
Input Frequency (kHz)
1000
SPURIOUS FREE DYNAMIC RANGE
and TOTAL HARMONIC DISTORTION
vs INPUT FREQUENCY
95
90
85
80 SFDR
75
THDT
70
65
60
T First nine harmonics
55 of an input frequency
50
1
10 100
Input Frequency (kHz)
–95
–90
–85
–80
–75
–70
–65
–60
–55
–50
1000
SIGNAL-TO-NOISE and
SIGNAL-TO-(NOISE+DISTORTION)
vs TEMPERATURE
0.3
0.2 fIN = 10kHz, –0.2dB)
0.1
0.
SNR
–0.1
–0.2
–0.3 SINAD
–0.4
–0.5
–40
–20
0 20 40 60
Temperature (°C)
80
100
®
ADS7834
6

6 Page









ADS7834PB pdf, datenblatt
11...111
11...110
11...101
FS = Full-Scale Voltage = VREF
1 LSB = FS/4096
1 LSB
00...010
00...001
00...000
0V 2.499V(1)
Input Voltage(2) (V)
NOTES: (1) For external reference, value is VREF – 1 LSB. (2) Voltage
at converter input: +IN (–IN).
FIGURE 7. Ideal Input Voltages and Output Codes.
DSP INTERFACING
Figure 8 shows a timing diagram that might be used with a
typical digital signal processor such as a TI DSP. For the
buffered serial port (BSP) on the TMS320C54X family,
CONV would tied to BFSX, CLK would be tied to BCLKX,
and DATA would be tied to BDR.
SPI/QSPI INTERFACING
Figure 9 shows the timing diagram for a typical serial
peripheral interface (SPI) or queued serial peripheral inter-
face (QSPI). Such interfaces are found on a number of
microcontrollers form various manufacturers. CONV would
be tied to a general purpose I/O pin (SPI) or to a PCX pin
(QSPI), CLK would be tied to the serial clock, and DATA
would be tied to the serial input data pin such as MISO
(master in slave out).
Note the time tDRP shown in Figure 9. This represents the
maximum amount of time between CONV going LOW and
the start of the conversion clock. Since CONV going LOW
places the sample and hold in the hold mode and because the
hold capacitor loses charge over time, there is a requirement
that time tDRP be met as well as the maximum clock period
(tCKP).
LAYOUT
For optimum performance, care should be taken with the
physical layout of the ADS7834 circuitry. This is particu-
larly true if the CLK input is approaching the maximum
input rate.
The basic SAR architecture is sensitive to glitches or sudden
changes on the power supply, reference, ground connec-
tions, and digital inputs that occur just prior to latching the
output of the analog comparator. Thus, during any single
conversion for an n-bit SAR converter, there are n “win-
dows” in which large external transient voltages can easily
affect the conversion result. Such glitches might originate
from switching power supplies, nearby digital logic, and
high power devices. The degree of error in the digital output
depends on the reference voltage, layout, and the exact
timing of the external event. The error can change if the
external event changes in time with respect to the CLK
input.
CONV
CLK 15
16
DATA
12 3
D11
(MSB)
D10
FIGURE 8. Typical DSP Interface Timing.
12 13 14
D1
D0
(LSB)
15 16
1 234
D11
(MSB)
D10
D9
CONV
tDRP
CLK
DATA
123 4
D11
(MSB)
D10
FIGURE 9. Typical SPI/QSPI Interface Timing.
®
ADS7834
13 14 15
D1
D0
(LSB)
16
12
tACQ
1 23
D11
(MSB)

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