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ADS7825P Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7825P
Beschreibung 4 Channel/ 16-Bit Sampling CMOS A/D Converter
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 16 Seiten
ADS7825P Datasheet, Funktion
®
ADS7825
ADS7825
ADS7825
www.burr-brown.com/databook/ADS7825.html
4 Channel, 16-Bit Sampling CMOS A/D Converter
FEATURES
q 25µs max SAMPLING AND CONVERSION
q SINGLE +5V SUPPLY OPERATION
q PIN-COMPATIBLE WITH 12-BIT ADS7824
q PARALLEL AND SERIAL DATA OUTPUT
q 28-PIN 0.3" PLASTIC DIP AND SOIC
q ±2.0 LSB max INL
q 50mW max POWER DISSIPATION
q 50µW POWER DOWN MODE
q ±10V INPUT RANGE, FOUR CHANNEL
MULTIPLEXER
q CONTINUOUS CONVERSION MODE
DESCRIPTION
The ADS7825 can acquire and convert 16 bits to
within ±2.0 LSB in 25µs max while consuming only
50mW max. Laser-trimmed scaling resistors provide
the standard industrial ±10V input range and channel-
to-channel matching of ±0.1%. The ADS7825 is a
low-power 16-bit sampling A/D with a four channel
input multiplexer, S/H, clock, reference, and a
parallel/serial microprocessor interface. It can be con-
figured in a continuous conversion mode to sequen-
tially digitize all four channels. The 28-pin ADS7825
is available in a plastic 0.3" DIP and in a SOIC, both
fully specified for operation over the industrial –40°C
to +85°C range.
AIN0
AIN1
AIN2
AIN3
40k
20k
40k
20k
40k
20k
40k
20k
Continuous Conversion
Channel
CONTC
A0 A1
R/C
Clock
8k
Successive Approximation Register
and Control Logic
CS
PWRD
CDAC
8k
8k
8k
CAP
REF
Buffer
6k
Internal
+2.5V Ref
Comparator
Serial
Data
Out
or
Parallel
Data
Out
8
BUSY
DATACLK
SDATA
D7-D0
BYTE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1996 Burr-Brown Corporation
PDS-11304B
APriDnteSd in7U8.S2.A5. October, 1997
®






ADS7825P Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, fS = 40kHz, VS1 = VS2 = +5V, using internal reference, unless otherwise noted.
110
105
100
95
90
85
80
–50
A. C. PARAMETERS vs TEMPERATURE
(fIN = 1kHz, –0.1dB)
SFDR
SNR
THD
SINAD
–25 0
25 50
Temperature (°C)
75
–110
–105
–100
–95
–90
–85
–80
100
POWER SUPPLY RIPPLE SENSITIVITY
INL/DNL DEGRADATION PER LSB OF P-P RIPPLE
1
10–1
10–2
10–3
INL
10–4
10–5
101
DNL
102 103 104 105 106
Power Supply Ripple Frequency (Hz)
107
2.520
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
–50
INTERNAL REFERENCE VOLTAGE
vs TEMPERATURE
–25 0
25 50 75
Temperature (°C)
100
3
2 All Codes INL
1
0
–1
–2
–3
0
8192 16384
24576 32768 40960
Decimal Code
49152
57344
65535
3
2 All Codes DNL
1
0
–1
–2
–3
0
8192 16384
24576 32768 40960
Decimal Code
49152
57344
65535
2
BPZ Error
1
0
–1
–2
0.2
+FS Error
0
ENDPOINT ERRORS
–0.2
0.2
–FS Error
0
–0.2
–50
20.4
–25 0
25 50 75
Temperature (°C)
CONVERSION TIME vs TEMPERATURE
100
20.2
20
19.8
19.6
–50
–25
0
25 50 75 100
Temperature (°C)
®
ADS7825
6

6 Page









ADS7825P pdf, datenblatt
READING DATA
PARALLEL OUTPUT
To use the parallel output, tie PAR/SER (pin 20) HIGH. The
parallel output will be active when R/C (pin 22) is HIGH and
CS (pin 23) is LOW. Any other combination of CS and R/C
will tri-state the parallel output. Valid conversion data can be
read in two 8-bit bytes on D7-D0 (pins 9-13 and 15-17). When
BYTE (pin 21) is LOW, the 8 most significant bits will be
valid with the MSB on D7. When BYTE is HIGH, the 8 least
significant bits will be valid with the LSB on D0. BYTE can
be toggled to read both bytes within one conversion cycle.
Upon initial power up, the parallel output will contain
indeterminate data.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. Valid data
from conversion ‘n’ will be available on D7-D0 (pins 9-13
and 15-17). BUSY going HIGH can be used to latch the
data. Refer to Table II and Figures 2 and 3 for timing
constraints.
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n – 1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to read data
beyond 12µs after the start of conversion ‘n’ until BUSY
(pin 24) goes HIGH; this may result in reading invalid data.
Refer to Table II and Figures 2 and 3 for timing constraints.
SERIAL OUTPUT
When PAR/SER (pin 20) is LOW, data can be clocked out
serially with the internal data clock or an external data clock.
When EXT/INT (pin 12) is LOW, DATACLK (pin 15) is an
output and is always active regardless of the state of CS (pin
23) and R/C (pin 22). The SDATA output is active when
BUSY (pin 24) is LOW. Otherwise, it is in a tri-state
condition. When EXT/INT is HIGH, DATACLK is an input.
The SDATA output is active when CS is LOW and R/C is
HIGH. Otherwise, it is in a tri-state condition. Regardless of
the state of EXT/INT, SYNC (pin 13) is an output and always
active, while TAG (pin 17) is always an input.
INTERNAL DATA CLOCK (During A Conversion)
To use the internal data clock, tie EXT/INT (pin 12) LOW.
The combination of R/C (pin 22) and CS (pin 23) LOW will
initiate conversion ‘n’ and activate the internal data clock
(typically 900kHz clock rate). The ADS7825 will output 16
bits of valid data, MSB first, from conversion ‘n – 1’ on
SDATA (pin 16), synchronized to 16 clock pulses output on
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t7 + t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
DESCRIPTION
Convert Pulse Width
Start of Conversion to New Data Valid
Start of Conversion to BUSY LOW
BUSY LOW
End of Conversion to BUSY HIGH
Aperture Delay
Conversion Time
Acquisition Time
Throughput Time
Bus Relinquish Time
Data Valid to BUSY HIGH
Start of Conversion to Previous Data Not Valid
Bus Access Time and BYTE Delay
Start of Conversion to DATACLK Delay
DATACLK Period
Data Valid to DATACLK HIGH
DATACLK LOW to Data Not Valid
External DATACLK Period
External DATACLK HIGH
External DATACLK LOW
CS LOW and R/C HIGH to External DATACLK HIGH (Enable Clock)
R/C to CS Setup Time
CS HIGH or R/C LOW to External DATACLK HIGH (Disable Clock)
DATACLK HIGH to SYNC HIGH
DATACLK HIGH to Valid Data
Start of Conversion to SDATA Active
End of Conversion to SDATA Tri-State
CS LOW and R/C HIGH to SDATA Active
CS HIGH or R/C LOW to SDATA Tri-State
BUSY HIGH to Address Valid
Address Valid to BUSY LOW
MIN
0.04
10
20
12
20
400
100
50
40
25
10
25
15
25
500
TYP
20
20
90
40
20
4
60
20
1.4
1.1
75
600
MAX
12
21
85
21
21
5
25
83
83
35
55
83
83
83
83
20
UNITS
µs
µs
ns
µs
ns
ns
µs
µs
µs
ns
ns
µs
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TABLE II. Conversion, Data, and Address Timing. TA = –40°C to +85°C.
®
ADS7825
12

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