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ADS7813PB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7813PB
Beschreibung Low-Power/ Serial 16-Bit Sampling ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 17 Seiten
ADS7813PB Datasheet, Funktion
® ADS7813
ADS7813
ADS7813
Low-Power, Serial 16-Bit Sampling
ANALOG-TO-DIGITAL CONVERTER
FEATURES
DESCRIPTION
q 20µs max CONVERSION TIME
q SINGLE +5V SUPPLY OPERATION
q PIN-COMPATIBLE WITH 12-BIT ADS7812
q EASY-TO-USE SERIAL INTERFACE
q 16-PIN 0.3" PLASTIC DIP AND SOIC
q ±2.0LSB max INL
q 87dB min SINAD
q USES INTERNAL OR EXTERNAL
REFERENCE
q MULTIPLE INPUT RANGES
q 35mW max POWER DISSIPATION
q NO MISSING CODES
q 50µW POWER DOWN MODE
APPLICATIONS
The ADS7813 is a low-power, single +5V supply, 16-
bit sampling analog-to-digital converter. It contains a
complete 16-bit capacitor-based SAR A/D with a
sample/hold, clock, reference, and serial data inter-
face.
The converter can be configured for a variety of input
ranges including ±10V, ±5V, 0V to 10V, and 0.5V to
4.5V. A high impedance 0.3V to 2.8V input range is
also available (input impedance > 10M). For most
input ranges, the input voltage can swing to +16.5V or
–16.5V without damage to the converter.
A flexible SPI compatible serial interface allows data
to be synchronized to an internal or external clock.
The ADS7813 is specified at a 40kHz sampling rate
over the –40°C to +85°C temperature range. It is
available in a 16-pin 0.3" plastic DIP or a 16-lead
SOIC package.
q MEDICAL INSTRUMENTATION
q DATA ACQUISITION SYSTEMS
q ROBOTICS
q INDUSTRIAL CONTROL
q TEST EQUIPMENT
q DIGITAL SIGNAL PROCESSING
q DSP SERVO CONTROL
BUSY
PWRD
CONV
CS
Successive Approximation Register and Control Logic
Clock
R1IN
R2IN
R3IN
BUF
CAP
REF
40k(1)
8k(1)
20k(1)
CDAC
Buffer
4k(1)
Internal
+2.5V Ref
Comparator
Serial
Data
Out
EXT/INT
DATACLK
DATA
NOTE: (1) Actual value may vary ±30%.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1997 Burr-Brown Corporation
PDS-11302A
APDrinSted7in8U1.S3.A. March, 1997
®






ADS7813PB Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, fS = 40kHz, VS = +5V, ±10V input range, using internal reference, unless otherwise noted.
2
1
0
–1
–2
2
1
0
–1
–2
8000h
ILE AND DLE AT –40°C
C000h
0000h
Hex BTC Code
4000h
7FFFh
2
1
0
–1
–2
2
1
0
–1
–2
8000h
ILE AND DLE AT +85°C
C000h
0000h
Hex BTC Code
4000h
7FFFh
2
1
0
–1
–2
2
1
0
–1
–2
8000h
ILE AND DLE AT +25°C
C000h
0000h
Hex BTC Code
4000h
7FFFh
POWER SUPPLY RIPPLE SENSITIVITY
ILE/DLE DEGRADATION PER LSB OF P-P RIPPLE
1
10–1
10–2
10–3
ILE
10–4
10–5
101
DLE
102 103 104 105 106
Power Supply Ripple Frequency (Hz)
107
®
ADS7813
6

6 Page









ADS7813PB pdf, datenblatt
External DATACLK Active After the Conversion
and During the Next Conversion
Figure 8 shows a method that is a hybrid of the two previous
approaches. This method works very well for microcontrollers
that do serial transfers 8 bits at a time and for slower
microcontrollers. For example, if the fastest serial clock that
the microcontroller can produce is 1µs, the approach shown
in Figure 6 would result in a diminished throughput (26kHz
maximum conversion rate). The method described in Figure
7 could not be used without risk of affecting the conversion
result (the clock would have to be active after time t2). The
approach in Figure 8 results in an improved throughput rate
(33kHz maximum with a 1µs clock) and DATACLK is not
active after time t2.
COMPATIBILITY WITH THE ADS7812
The only difference between the ADS7812 and the ADS7813
is in the internal control logic and the digital interface. Since
the ADS7812 is a 12-bit converter, the internal shift register
is 12 bits wide. In addition, only 12-bit decisions are made
during the conversion. Thus, the ADS7812’s conversion
time is approximately 75% of the ADS7813’s.
In the internal DATACLK mode, the ADS7812 produces 12
DATACLK periods during the conversion instead of the
ADS7813’s 16 (see Figure 5). In the external DATACLK
mode, the ADS7812 can accept 16 clock periods on
DATACLK. At the start of the 13th clock cycle, the DATA
output will go LOW and remain LOW. Thus, Figures 6, 7,
8, and the associated times in Table II can also be used for
the ADS7812, but the last four bits of the conversion result
will be zero.
CHIP SELECT (CS)
The CS input allows the digital outputs of the ADS7812 to
be disabled and gates the external DATACLK signal when
EXT/INT is HIGH. See Figure 9 for the enable and disable
time associated with CS and Figure 3 for a block diagram of
the ADS7813’s logic. The digital outputs can be disabled at
any time.
Note that a conversion is initiated on the falling edge of
CONV even if CS is HIGH. If the EXT/INT input is LOW
(internal DATACLK) and CS is HIGH during the entire
conversion, the previous conversion result will be lost (the
serial transmission occurs but DATA and DATACLK are
disabled).
CS
BUSY, DATA,
DATACLK(1)
t26
HI-Z
t27
Active
HI-Z
NOTE: (1) DATACLK is an output only when EXT/INT is LOW.
FIGURE 9. Enable and Disable Timing for Digital Outputs.
ANALOG INPUT
The ADS7813 offers a number of input ranges. This is
accomplished by connecting the three input resistors to
either the analog input (VIN), to ground (GND), or to the
2.5V reference buffer output (BUF). Table I shows the input
ranges that are typically used in most data acquisition
applications. These ranges are all guaranteed to meet the
specifications given in the Specifications table. Table IV
contains a complete list of ideal input ranges, associated
input connections, and comments regarding the range.
ANALOG
INPUT
RANGE (V)
0.3125 to 2.8125
–0.417 to 2.916
0.417 to 3.750
±3.333
–15 to 5
±10
0.833 to 7.5
–2.5 to 17.5
2.5 to 22.5
0 to 2.857
–1 to 3
0 to 4
–6.25 to 3.75
0 to 10
0.357 to 3.214
–0.5 to 3.5
0.5 to 4.5
±5
1.25 to 11.25
CONNECT
R1IN
TO
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
BUF
BUF
BUF
BUF
BUF
GND
GND
GND
GND
GND
CONNECT
R2IN
TO
VIN
VIN
VIN
BUF
BUF
BUF
GND
GND
GND
VIN
VIN
VIN
BUF
GND
VIN
VIN
VIN
BUF
GND
TABLE IV. Complete List of Ideal Input Ranges.
®
ADS7813
CONNECT
R3IN
TO
VIN
BUF
GND
VIN
BUF
GND
VIN
BUF
GND
VIN
BUF
GND
VIN
VIN
VIN
BUF
GND
VIN
VIN
INPUT
IMPEDANCE
(k)
> 10,000
26.7
26.7
21.3
45.7
45.7
21.3
45.7
45.7
45.7
21.3
21.3
26.7
26.7
45.7
21.3
21.3
26.7
26.7
COMMENT
Guaranteed offset and gain
VIN cannot go below GND – 0.3V
Offset and gain not guaranteed
Guaranteed offset and gain
Offset and gain not guaranteed
Guaranteed offset and gain
Offset and gain not guaranteed
Exceeds absolute maximum VIN
Exceeds absolute maximum VIN
Offset and gain not guaranteed
VIN cannot go below GND – 0.3V
Guaranteed offset and gain
Offset and gain not guaranteed
Guaranteed offset and gain
Offset and gain not guaranteed
VIN cannot go below GND – 0.3V
Guaranteed offset and gain
Guaranteed offset and gain
Offset and gain not guaranteed
12

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