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ADS7807UB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7807UB
Beschreibung Low-Power 16-Bit Sampling CMOS ANALOG-to-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 19 Seiten
ADS7807UB Datasheet, Funktion
® ADS7807
Low-Power 16-Bit Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
q 35mW max POWER DISSIPATION
q 50µW POWER DOWN MODE
q 25µs max ACQUISITION AND
CONVERSION
q ±1.5LSB max INL
q DNL: 16 bits “No Missing Codes”
q 86dB min SINAD WITH 1kHz INPUT
q ±10V, 0V TO +5V, AND 0V TO +4V INPUT
RANGES
q SINGLE +5V SUPPLY OPERATION
q PARALLEL AND SERIAL DATA OUTPUT
q PIN-COMPATIBLE WITH 12-BIT ADS7806
q USES INTERNAL OR EXTERNAL
REFERENCE
q 28-PIN 0.3" PLASTIC DIP AND SOIC
DESCRIPTION
The ADS7807 is a low-power, 16-bit, sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 16-bit, capacitor-based, SAR A/D with S/H,
clock, reference, and microprocessor interface with
parallel and serial output drivers.
The ADS7807 can acquire and convert 16-bits to
within ±1.5LSB in 25µs max while consuming only
35mW max. Laser-trimmed scaling resistors provide
standard industrial input ranges of ±10V and 0V to
+5V. In addition, a 0V to +4V range allows develop-
ment of complete single supply systems.
The 28-pin ADS7807 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C temperature range.
R1IN
40k
R2IN
20k
10k
CAP
40k
REF
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
Power
Down
CDAC
Comparator
Buffer
6k
Internal
+2.5V Ref
Reference
Power
Down
Parallel
and
Serial
Data
Out
BUSY
Serial Data
Clock
Serial Data
Parallel Data
8
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1159C
Printed in U.S.A. November, 1994






ADS7807UB Datasheet, Funktion
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, fS = 40kHz, VDIG = VANA = +5V, using internal reference and fixed resistors shown in Figure 7b, unless otherwise specified.
3
2 All Codes INL
1
0
–1
–2
–3
0 8192 16384
24576 32768 40960
Decimal Code
49152
57344
65535
3
2 All Codes DNL
1
0
–1
–2
–3
0 8192 16384
24576 32768 40960
Decimal Code
49152
57344
65535
POWER SUPPLY RIPPLE SENSITIVITY
INL/DNL DEGRADATION PER LSB OF P-P RIPPLE
1
10–1
10–2
10–3
INL
10–4
10–5
101
DNL
102 103 104 105 106
Power Supply Ripple Frequency (Hz)
107
ENDPOINT ERRORS (20V BIPOLAR RANGE)
3
2
BPZ Error
1
0
–1
–2
0.20 +FS Error
0
–0.20
0.20 –FS Error
0
–0.20
–75 –50 –25
0 25 50 75
Temperature (°C)
100 125
150
ENDPOINT ERRORS (UNIPOLAR RANGES)
3
2 UPO Error
1
0
–1
–2
0.40
+FS Error (4V Range)
0.20
0
0.40
+FS Error (5V Range)
0.20
0
–75 –50 –25
0 25 50 75
Temperature (°C)
100 125
150
2.520
INTERNAL REFERENCE VOLTAGE vs TEMPERATURE
2.515
2.510
2.505
2.500
2.495
2.490
2.485
2.480
–75 –50 –25
0 25 50 75 100 125 150
Temperature (°C)
CONVERSION TIME vs TEMPERATURE
19.4
19.2
19
18.8
18.6
–75 –50 –25
0 25 50 75 100 125 150
Temperature (°C)
®
ADS7807
6

6 Page









ADS7807UB pdf, datenblatt
EXTERNAL
DATACLK
CS
R/C
BUSY
DATA
TAG
t17
t18
t19
t22
t21 t20
t1
t3
Bit 15 (MSB)
Tag 0
Tag 1
t20
t11
Bit 0 (LSB)
Tag 0
Tag 1
Tag 16
Tag 17
Tag 18
FIGURE 6. Conversion and Read Timing with External Clock (EXT/INT tied HIGH) Read During a Conversion.
EXTERNAL DATA CLOCK
(After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 24) will go HIGH. With CS
LOW and R/C HIGH, valid data from conversion ‘n’ will be
output on SDATA (pin 19) synchronized to the external data
clock input on DATACLK (pin 18). The MSB will be valid
on the first falling edge and the second rising edge of the
external data clock. The LSB will be valid on the 16th falling
edge and 17th rising edge of the data clock. TAG (pin 20)
will input a bit of data for every external clock pulse. The
first bit input on TAG will be valid on SDATA on the 17th
falling edge and the 18th rising edge of DATACLK; the
second input bit will be valid on the 18th falling edge and the
19th rising edge, etc. With a continuous data clock, TAG
data will be output on SDATA until the internal output
registers are updated with the results from the next conver-
sion. Refer to Table VI and Figure 5.
EXTERNAL DATA CLOCK
(During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 12µs
after the start of conversion ‘n’. Do not attempt to clock out
data from 12µs after the start of conversion ‘n’ until BUSY
(pin 24) rises; this will result in data loss. NOTE: For the
best possible performance when using an external data
clock, data should not be clocked out during a conversion.
The switching noise of the asynchronous data clock can
cause digital feedthrough degrading the converter’s perfor-
mance. Refer to Table VI and Figure 6.
TAG FEATURE
TAG (Pin 20) inputs serial data synchronized to the external
or internal data clock.
When using an external data clock, the serial bit stream input
on TAG will follow the LSB output on SDATA until the
internal output register is updated with new conversion
results. See Table VI and Figures 5 and 6.
The logic level input on TAG for the first rising edge of the
internal data clock will be valid on SDATA after all 16 bits
of valid data have been output.
INPUT RANGES
The ADS7807 offers three input ranges: standard ±10V and
0-5V, and a 0-4V range for complete, single supply systems.
Figures 7a and 7b show the necessary circuit connections for
implementing each input range and optional offset and gain
adjust circuitry. Offset and full scale error(1) specifications
are tested and guaranteed with the fixed resistors shown in
Figure 7b. Adjustments for offset and gain are described in
the Calibration section of this data sheet.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).
The input impedance, summarized in Table II, results from the
combination of the internal resistor network shown on the
front page of the product data sheet and the external resistors
®
ADS7807
NOTE: (1) Full scale error includes offset and gain errors measured at both
+FS and –FS.
12

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