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ADS7804UB Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS7804UB
Beschreibung 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 10 Seiten
ADS7804UB Datasheet, Funktion
® ADS7804
ADS7804
ADS7804
DEMO BOARD
AVAILABLE
12-Bit 10µs Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
q 100kHz min SAMPLING RATE
q STANDARD ±10V INPUT RANGE
q 72dB min SINAD WITH 45kHz INPUT
q ±0.45 LSB max INL
q DNL: 12 Bits “No Missing Codes”
q SINGLE +5V SUPPLY OPERATION
q PIN-COMPATIBLE WITH 16-BIT ADS7805
q USES INTERNAL OR EXTERNAL
REFERENCE
q COMPLETE WITH S/H, REF, CLOCK, ETC.
q FULL PARALLEL DATA OUTPUT
q 100mW max POWER DISSIPATION
q 28-PIN 0.3" PLASTIC DIP AND SOIC
DESCRIPTION
The ADS7804 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit, capacitor-based, SAR A/D with S/H,
reference, clock, interface for microprocessor use, and
three-state output drivers.
The ADS7804 is specified at a 100kHz sampling rate,
and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide an industry-
standard ±10V input range, while the innovative de-
sign allows operation from a single +5V supply, with
power dissipation under 100mW.
The 28-pin ADS7804 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C range.
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
±10V Input
20k
10k4k
CAP
REF
CDAC
Buffer
4k
Internal
+2.5V Ref
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1156C
Printed in U.S.A. February, 1996






ADS7804UB Datasheet, Funktion
READING DATA
The ADS7804 outputs full or byte-reading parallel data in
Binary Two’s Complement data output format. The parallel
output will be active when R/C (pin 24) is HIGH and CS
(pin 25) is LOW. Any other combination of CS and R/C will
tri-state the parallel output. Valid conversion data can be
read in a full parallel, 12-bit word or two 8-bit bytes on pins
6-13 and pins 15-22. BYTE (pin 23) can be toggled to read
both bytes within one conversion cycle. Refer to Table III
for ideal output codes and Figure 2 for bit locations relative
to the state of BYTE.
DESCRIPTION ANALOG INPUT
Full Scale Range
±10V
Least Significant
Bit (LSB)
4.88mV
+Full Scale
(10V – 1LSB)
9.99512V
Midscale
0V
One LSB below
Midscale
–4.88mV
–Full Scale
–10V
DIGITAL OUTPUT
BINARY TWO’S COMPLEMENT
BINARY CODE HEX CODE
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
7FF
000
FFF
800
Table III. Ideal Input Voltages and Output Codes.
PARALLEL OUTPUT (After a Conversion)
After conversion ‘n’ is completed and the output registers
have been updated, BUSY (pin 26) will go HIGH. Valid data
from conversion ‘n’ will be available on D11-D0 (pin 6-13
and 15-18 when BYTE is LOW). BUSY going HIGH can be
used to latch the data. Refer to Table IV and Figures 3 and
5 for timing specifications.
PARALLEL OUTPUT (During a Conversion)
After conversion ‘n’ has been initiated, valid data from
conversion ‘n-1’ can be read and will be valid up to 16µs
after the start of conversion ‘n’. Do not attempt to read data
from 16µs after the start of conversion ‘n’ until BUSY (pin
26) goes HIGH; this may result in reading invalid data.
Refer to Table IV and Figures 3 and 5 for timing specifica-
tions.
Note! For the best possible performance, data should not be
read during a conversion. The switching noise of the asyn-
chronous data transfer can cause digital feedthrough degrad-
ing the converter’s performance.
The number of control lines can be reduced by tieing CS
LOW while using R/C to initiate conversions and activate
the output mode of the converter. See Figure 3.
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t7 + t6
t12
t13
t14
DESCRIPTION
Convert Pulse Width
Data Valid Delay after R/C LOW
BUSY Delay from R/C LOW
BUSY LOW
BUSY Delay after
End of Conversion
Aperture Delay
Conversion Time
Acquisition Time
Bus Relinquish Time
BUSY Delay after Data Valid
Previous Data Valid
after R/C LOW
Throughput Time
R/C to CS Setup Time
Time Between Conversions
Bus Access Time
and BYTE Delay
MIN TYP MAX UNITS
40 6000 ns
8 µs
65 ns
8 µs
220 ns
40
7.6
10 35
50 200
7.4
8
2
83
ns
µs
µs
ns
ns
µs
9 10 µs
10 ns
10 µs
10 83 ns
TABLE IV. Conversion Timing.
BYTE LOW
Bit 11 (MSB) 6
Bit 10 7
Bit 9 8
Bit 8 9
Bit 7 10
Bit 6 11
Bit 5 12
Bit 4 13
14
ADS7804
23
22 LOW
21 LOW
20 LOW
19 LOW
18 Bit 0 (LSB)
17 Bit 1
16 Bit 2
15 Bit 3
BYTE HIGH
Bit 3 6
23
+5V
Bit 2 7
Bit 1 8
ADS7804
22 Bit 4
21 Bit 5
Bit 0 (LSB) 9
20 Bit 6
LOW 10
19 Bit 7
LOW 11
18 Bit 8
LOW 12
17 Bit 9
LOW 13
16 Bit 10
14 15 Bit 11
FIGURE 2. Bit Locations Relative to State of BYTE (pin 23).
®
ADS7804
6

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