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PDF ADS7804 Data sheet ( Hoja de datos )
| Número de pieza | ADS7804 | |
| Descripción | 12-Bit 10ms Sampling CMOS ANALOG-to-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADS7804 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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® ADS7804
ADS7804
ADS7804
DEMO BOARD
AVAILABLE
12-Bit 10µs Sampling CMOS
ANALOG-to-DIGITAL CONVERTER
FEATURES
q 100kHz min SAMPLING RATE
q STANDARD ±10V INPUT RANGE
q 72dB min SINAD WITH 45kHz INPUT
q ±0.45 LSB max INL
q DNL: 12 Bits “No Missing Codes”
q SINGLE +5V SUPPLY OPERATION
q PIN-COMPATIBLE WITH 16-BIT ADS7805
q USES INTERNAL OR EXTERNAL
REFERENCE
q COMPLETE WITH S/H, REF, CLOCK, ETC.
q FULL PARALLEL DATA OUTPUT
q 100mW max POWER DISSIPATION
q 28-PIN 0.3" PLASTIC DIP AND SOIC
DESCRIPTION
The ADS7804 is a complete 12-bit sampling A/D
using state-of-the-art CMOS structures. It contains a
complete 12-bit, capacitor-based, SAR A/D with S/H,
reference, clock, interface for microprocessor use, and
three-state output drivers.
The ADS7804 is specified at a 100kHz sampling rate,
and guaranteed over the full temperature range. Laser-
trimmed scaling resistors provide an industry-
standard ±10V input range, while the innovative de-
sign allows operation from a single +5V supply, with
power dissipation under 100mW.
The 28-pin ADS7804 is available in a plastic 0.3" DIP
and in an SOIC, both fully specified for operation over
the industrial –40°C to +85°C range.
Clock
Successive Approximation Register and Control Logic
R/C
CS
BYTE
BUSY
±10V Input
20kΩ
10kΩ 4kΩ
CAP
REF
CDAC
Buffer
4kΩ
Internal
+2.5V Ref
Comparator
Output
Latches
and
Three
State
Drivers
Three
State
Parallel
Data
Bus
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1992 Burr-Brown Corporation
PDS-1156C
Printed in U.S.A. February, 1996
1 page  
BASIC OPERATION
Figure 1 shows a basic circuit to operate the ADS7804 with
a full parallel data output. Taking R/C (pin 24) LOW for a
minimum of 40ns (6µs max) will initiate a conversion.
BUSY (pin 26) will go LOW and stay LOW until the
conversion is completed and the output registers are up-
dated. Data will be output in Binary Two’s Complement
with the MSB on pin 6. BUSY going HIGH can be used to
latch the data. All convert commands will be ignored while
BUSY is LOW.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).
STARTING A CONVERSION
The combination of CS (pin 25) and R/C (pin 24) LOW for
a minimum of 40ns immediately puts the sample/hold of the
ADS7804 in the hold state and starts conversion ‘n’. BUSY
(pin 26) will go LOW and stay LOW until conversion ‘n’ is
completed and the internal output register has been updated.
All new convert commands during BUSY LOW will be
ignored. CS and/or R/C must go HIGH before BUSY goes
HIGH or a new conversion will be initiated without suffi-
cient time to acquire a new signal.
The ADS7804 will begin tracking the input signal at the end
of the conversion. Allowing 10µs between convert com-
mands assures accurate acquisition of a new signal. Refer to
Table II for a summary of CS, R/C, and BUSY states and
Figures 3 through 5 for timing diagrams.
CS and R/C are internally OR’d and level triggered. There
is not a requirement which input goes LOW first when
initiating a conversion. If, however, it is critical that CS or
R/C initiates conversion ‘n’, be sure the less critical input is
LOW at least 10ns prior to the initiating input.
To reduce the number of control pins, CS can be tied LOW
using R/C to control the read and convert modes. This will
have no effect when using the internal data clock in the serial
output mode. However, the parallel output will become
active whenever R/C goes HIGH. Refer to the Reading
Data section.
CS R/C BUSY OPERATION
1 X X None. Databus is in Hi-Z state.
↓ 0 1 Initiates conversion “n”. Databus remains
in Hi-Z state.
0 ↓ 1 Initiates conversion “n”. Databus enters Hi-Z
state.
0 1 ↑ Conversion “n” completed. Valid data from
conversion “n” on the databus.
↓ 1 1 Enables databus with valid data from
conversion “n”.
↓ 1 0 Enables databus with valid data from
conversion “n-1”(1). Conversion n in process.
0 ↑ 0 Enables databus with valid data from
conversion “n-1”(1). Conversion “n” in process.
0 0 ↑ New conversion initiated without acquisition
of a new signal. Data will be invalid. CS and/or
R/C must be HIGH when BUSY goes HIGH.
X X 0 New convert commands ignored. Conversion
“n” in process.
NOTE: (1) See Figures 2 and 3 for constraints on data valid from
conversion “n-1”.
Table II. Control Line Functions for “Read” and “Convert”.
200Ω
33.2kΩ
B15 (MSB)
B14
B13
B12
B11
B10
B9
B8
1
+2
2.2µF
3
+
2.2µF
4
5
6
7
8
9
10
11
12
13
14
ADS7804
28
27
26
25
24
23
22
21
20
19
18
17
16
15
+ + +5V
0.1µF 10µF
Convert Pulse
B0 (LSB)
B1
B2
B3
B4
B5
B6
B7
40ns min
6µs max
FIGURE 1. Basic Operation.
®
5 ADS7804
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ADS7804.PDF ] | |
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