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PDF ADS7803BP Data sheet ( Hoja de datos )
| Número de pieza | ADS7803BP | |
| Descripción | Autocalibrating/ 4-Channel/ 12-Bit ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
| Logotipo |  |
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® ADS7803
Autocalibrating, 4-Channel, 12-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q LOW POWER: 10mW plus Power Down
q SIGNAL-TO-(NOISE + DISTORTION)
RATIO OVER TEMPERATURE:
69dB min with fIN = 1kHz
66dB min with fIN = 50kHz
q FAST CONVERSION TIME: 8.5µs
Including Acquisition (117kHz Sampling
Rate)
q DC PERFORMANCE OVER
TEMPERATURE:
±3/4 LSB max Total Error
±1/4 LSB max Channel Mismatch
q FOUR-CHANNEL INPUT MULTIPLEXER
q SINGLE SUPPLY: +5V
q PIN COMPATIBLE WITH ADC7802
DESCRIPTION
The ADS7803 is a monolithic CMOS 12-bit analog-
to-digital converter with internal sample/hold and four-
channel multiplexer. It is designed and tested for full
dynamic performance with input signals to 50kHz. An
autocalibration cycle guarantees a total unadjusted
error within ±3/4LSB over the specified temperature
range, eliminating the need for offset or gain adjust-
ment. The 5V single-supply requirements and stan-
dard CS, RD, and WR control signals make the part
easy to use in microprocessor applications. Conver-
sion results are available in two bytes through an 8-bit
three-state output bus.
The ADS7803 is available in a 28-pin plastic DIP and
28-lead PLCC, fully specified for operation over the
industrial –40°C to +85°C temperature range.
A0 Address
Calibration
Latch and
Microcontroller
A1 Decoder
and Memory
Clock
Control
Logic
CS
RD
WR
SFR
AIN0
AIN1
AIN2
AIN3
Analog
Multiplexer
Capacitor Array
Sampling ADC
VREF+ VREF–
Three-State
Input/Output
BUSY
8-Bit
Data Bus
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1991 Burr-Brown Corporation
PDS-1126A
Printed in U.S.A. August, 1993
1 page  
TYPICAL PERFORMANCE CURVES (CONT)
At VA = VD = VREF+ = 5V, VREF– = AGND = 0V, TA = +25°C, dynamic performance based on 2048 point FFTs , unless otherwise noted.
INTERNAL CLOCK FREQUENCY vs TEMPERATURE
1.15
INTERNAL CLOCK FREQUENCY vs RCLOCK
10
1.1
1.05
1
RCLOCK = 70kΩ
1
0.95
0.9
–50
–25 0
25 50
Ambient Temperature (°C)
75
100
0.1
10
100
RCLOCK (kΩ)
1k
THEORY OF OPERATION
OPERATION
ADS7803 uses the advantages of advanced CMOS technol-
ogy (logic density, stable capacitors, precision analog
switches, and low power consumption) to provide a precise
12-bit analog-to-digital converter with on-chip sampling and
four-channel analog-input multiplexer.
The input stage consists of an analog multiplexer with an
address latch to select from four input channels.
The converter stage consists of an advanced successive
approximation architecture using charge redistribution on a
capacitor network to digitize the input signal. A tempera-
ture-stabilized differential auto-zeroing circuit is used to
minimize offset errors in the comparator.
Linearity errors in the binary weighted main capacitor
network are corrected using a capacitor trim network and
correction factors stored in on-chip memory. The correction
terms are calculated by an on-chip microcontroller during a
calibration cycle, initiated either by power-up or by applying
an external calibration signal at any time. During conver-
sion, the correct trim capacitors are switched into the main
capacitor array as needed to correct the conversion accuracy.
With all of the capacitors in both the main array and the trim
array on the same chip, excellent stability is achieved, both
over temperature and over time.
For flexibility, timing circuits include both an internal clock
generator and an input for an external clock to synchronize
with external systems. Standard control signals and three-
state input/output registers simplify interfacing ADS7803 to
most micro-controllers, microprocessors or digital storage
systems.
The on-chip sampling provides excellent dynamic perfor-
mance for input signals to 50kHz, and has a full-power –3dB
bandwidth of 4MHz. Full control over sample-to-hold
timing is available for applications where this is critical.
BASIC OPERATION
Figure 1 shows the simple circuit required to operate
ADS7803 in the Transparent Mode, converting a single
input channel. A convert command on pin 20 (WR) starts a
conversion. Pin 22 (BUSY) will output a LOW during the
conversion process (including sample acquisition and con-
version), and rises only after the conversion is completed.
The two bytes of output data can then be read using pin 18
(RD) and pin 21 (HBE).
NC 1
2
SFR
AIN0
VA 28
AGND 27
10nF
+5V
+
10µF
0 –5V
Input
3 AIN1
4 AIN2
CAL 26 NC
A1 25
100kΩ
+5V
+
10µF
BUSY
5 AIN3
A0 24
10nF
6 VREF+ CLK 23
7 VREF– BUSY 22
8 DGND HBE 21
9
Data Bit 7 10
VD
D7
WR 20
CS 19
BUSY
High Byte
Enable
Command
Convert
Command
LOW Data Bit 6 11 D6
RD 18
Read Command
LOW
LOW
Data Bit 5 12 D5
Data Bit 4 13 D4
D0 17 Data Bit 0 Data Bit 8
(LSB)
D1 16 Data Bit 1 Data Bit 9
Data Bit 11 Data Bit 3 14
(MSB)
HBE Input HBE Input
HIGH
LOW
D3
D2 15 Data Bit 2 Data Bit 10
HBE Input HBE Input
LOW
HIGH
FIGURE 1. Basic Operation.
Finally, this performance is matched with the low-power
advantages of CMOS structures to allow a typical power
consumption of 10mW, with a 50µW power down option.
5
ADS7803
®
5 Page 
ADS7803
Output
5V
3kΩ
Test
Point
CL
(a) Load Circuit
Output VD
Enable
Gnd
tFALL
90%
50%
10%
VD
VOL
10%
t15
t14
(b) From LOW to Hi-Z, CL = 10pF
Output VD
Enable
Gnd
VD
10%
tRISE
90%
50%
t13
0.8V
VOL
(c) From Hi-Z to LOW, CL = 100pF
ADS7803
Output
3kΩ
Test
Point
CL
(a) Load Circuit
Output VD
Enable
Gnd
tFALL
90%
50%
10%
VOH 90%
Gnd
t15
t14
(b) From HIGH to Hi-Z, CL = 10pF
Output VD
Enable
Gnd
VOH
Gnd
10%
tRISE
90%
50%
t13
2.4V
(c) From Hi-Z to HIGH, CL = 100pF
FIGURE 8. Measuring Active LOW to/from Hi-Z State.
to reduce dynamic errors, since the reference provides pack-
ets of current as the successive approximation steps are
carried out.
VREF+ must not exceed VA. Although the accuracy is speci-
fied with VREF+ = 5V and VREF– = 0V, the converter can
function with VREF+ as low as 4.5V and VREF– as high as
1V.
As long as there is at least a 4.5V difference between VREF+
and VREF–, the absolute value of errors does not change
significantly, so that accuracy will typically be within ±1LSB
The power supply to the reference source needs to be
considered during system design to prevent VREF+ from
exceeding (or overshooting) VA, particularly at power-on.
Also, after power-on, if the reference is not stable within
42,425 clock cycles, an additional calibration cycle may be
needed.
POWER SUPPLIES
The digital and analog power supply lines to the ADS7803
should be bypassed with 10µF tantalum capacitors as close
to the part as possible. Although ADS7803 has excellent
FIGURE 9. Measuring Active HIGH to/from Hi-Z State.
power supply rejection, even for higher frequencies, linear
regulated power supplies are recommended.
Care should be taken to insure that VD does not come up
before VA, or permanent damage to the part may occur.
Analog
Input
50Ω
To ADS7803
5nF
VREF– (Normally 0V)
(a) Passive Low Pass Filter
Analog
Input
R OPA627
To ADS7803
C
VREF– (Normally 0V)
(b) Active Low Pass Filter
FIGURE 10. Input Signal Conditioning.
®
11 ADS7803
11 Page | ||
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| PDF Descargar | [ Datasheet ADS7803BP.PDF ] | |
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