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ADS5270IPFP Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS5270IPFP
Beschreibung 8-Channel/ 12-Bit/ 40MSPS ADC with Serial LVDS Interface
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 18 Seiten
ADS5270IPFP Datasheet, Funktion
ADS5270
SBAS293D − JANUARY 2004 − REVISED MAY 2004
8-Channel, 12-Bit, 40MSPS ADC
with Serial LVDS Interface
FEATURES
D Maximum Sample Rate: 40MSPS
D 12-Bit Resolution
D No Missing Codes
D Power Dissipation: 907mW
D CMOS Technology
D Simultaneous Sample-and-Hold
D 70.5dB SNR at 10MHz IF
D Internal and External References
D 3.3V Digital/Analog Supply
D Serialized LVDS Outputs
D Integrated Frame and Synch Patterns
D MSB and LSB First Modes
D Option to Double LVDS Clock Output Currents
D Pin- and Format-Compatible Family
D TQFP-80 PowerPADPackage
APPLICATIONS
D Portable Ultrasound Systems
D Tape Drives
D Test Equipment
D Optical Networking
DESCRIPTION
or LSB first. The bit coinciding with the rising edge of the 1x
clock output is the first bit of the word. Data is to be latched by
the receiver on both the rising and falling edges of the 6x clock.
The ADS5270 provides internal references, or can optionally
be driven with external references. Best performance can be
achieved through the internal reference mode.
The device is available in a PowerPAD TQFP-80 package and
is specified over a −40°C to +85°C operating range.
6X ADCLK
ADCLK
IN1P
IN1N
S/H
IN2P
IN2N
S/H
IN3P
IN3N
S/H
IN4P
IN4N
S/H
IN5P
IN5N
S/H
PLL
1X ADCLK
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
Serializer
Serializer
Serializer
Serializer
Serializer
LCLKP
LCLKN
ADCLKP
ADCLKN
OUT1P
OUT1N
OUT2P
OUT2N
OUT3P
OUT3N
OUT4P
OUT4N
OUT5P
OUT5N
The ADS5270 is a high-performance, 40MSPS, 8-channel,
parallel analog-to-digital converter (ADC). Internal references
are provided, simplifying system design requirements. Low
power consumption allows for the highest of system
integration densities. Serial LVDS (low-voltage differential
signaling) outputs reduce the number of interface lines and
package size.
An integrated phase lock loop multiplies the incoming ADC
sampling clock by a factor of 12. This 12x clock is used in the
process of serializing the data output from each channel. The
12x clock is also used to generate a 1x and a 6x clock, both
of which are transmitted as LVDS clock outputs. The 6x clock
is denoted by the differential pair LCLKP and LCLKN, while the
1x clock is denoted by ADCLKP and ADCLKN. The word
output of each ADC channel can be transmitted either as MSB
IN6P
IN6N
S/H
IN7P
IN7N
S/H
IN8P
IN8N
S/H
12−Bit
ADC
12−Bit
ADC
12−Bit
ADC
Serializer
Serializer
Serializer
Reference
Registers
Control
INT/EXT
OUT6P
OUT6N
OUT7P
OUT7N
OUT8P
OUT8N
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated
www.ti.com






ADS5270IPFP Datasheet, Funktion
ADS5270
SBAS293D − JANUARY 2004 − REVISED MAY 2004
SERIAL INTERFACE TIMING
ADDRESS
DATA
D7 D6 D5 D4 D3 D2 D1
0000
00
01
10
11
0
0
1
1
0001
D3 D2 D1
0XX
00X
01X
0010
D3 D2 D1
XXX
0011
D3 D2 D1
XXX
D3 D2 D1
0 1 0 0 MSB X X
0 1 0 1XXX
0 1 1 0XXX
DESCRIPTION
D0
0. LVDS BUFFERS
Normal ADC Output
Deskew Pattern
Sync Pattern
Custom Pattern
0 Output Current in LVDS = 3.5mA
1 Output Current in LVDS = 2.5mA
0 Output Current in LVDS = 4.5mA
1 Output Current in LVDS = 6.0mA
1. LSB/MSB MODE
D0 Default LVDS Clock Output Current
1 2X LVDS Clock Output Current
X LSB Mode
X MSB Mode
2. POWER-DOWN ADC CHANNELS
D0
X
Power-Down Channels 1 to 4; D3 is
for Channel 4 and D0 for Channel 1
3. POWER-DOWN ADC CHANNELS
D0
X
Power-Down Channels 5 to 8; D3 is
for Channel 8 and D0 for Channel 5
CUSTOM PATTERN (registers 4-6)
D0
X
X Bits for Custom Pattern
LSB
www.ti.com
REMARKS
Patterns Get Reversed in MSB First
Mode of LVDS
Example: 1010 Powers Down
Channels 4 and 2 and Keeps
Channels 1 and 3 Alive
TEST PATTERNS(1)
Deskew
101010101010
Sync
000000111111
Custom
Any 12-bit pattern that is defined in the custom pattern registers 4 to 6. The output comes out in the following order:
D0(4) D1(4) D2(4) D3(4) D0(5) D1(5) D2(5) D3(5) D0(6) D1(6) D2(6) D3(6)
where, for example, D0(4) refers to the D0 bit of register 4, etc.
(1) Default is LSB first. If MSB is selected the above patterns will be reversed.
6

6 Page









ADS5270IPFP pdf, datenblatt
ADS5270
SBAS293D − JANUARY 2004 − REVISED MAY 2004
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Typical values are at TA = 25°C, clock frequency = maximum specified, 50% clock duty cycle, AVDD = 3.3V, LVDD = 3.3V, −1dBFS,
ISET = 56k, internal voltage reference, and LVDS buffer current at 3.5mA per channel, unless otherwise noted.
DYNAMIC PERFORMANCE vs CLOCK FREQUENCY
95
90 fIN = 10MHz
SFDR
85
80
75
SNR
70
SINAD
65
60
55
20
25 30 35 40
Clock Frequency (MHz)
45
0.30
0.25
IAVDD, IDVDD vs CLOCK FREQUENCY
fIN = 5MHz
0.20
IAVDD
0.15
0.10
0.05
IDVDD
0
20
25 30 35 40
Clock Frequency (MHz)
POWER DISSIPATION vs TEMPERATURE
904
fIN = 5MHz
902
900
898
896
894
892
890
888
886
40
15 10
35
Temperature ( C)
60
85
45
12

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