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ADS1255IDBT Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS1255IDBT
Beschreibung Very Low Noise/ 24-Bit Analog-to-Digital Converter
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 39 Seiten
ADS1255IDBT Datasheet, Funktion
ADS1255
ADS1256
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
Very Low Noise, 24ĆBit
AnalogĆtoĆDigital Converter
FEATURES
DESCRIPTION
D 24 Bits, No Missing Codes
− All Data Rates and PGA Settings
D Up to 23 Bits Noise-Free Resolution
D ±0.0010% Nonlinearity (max)
D Data Output Rates to 30kSPS
D Fast Channel Cycling
− 18.6 Bits Noise-Free (21.3 Effective Bits)
at 1.45kHz
D One-Shot Conversions with Single-Cycle
Settling
D Flexible Input Multiplexer with Sensor Detect
− Four Differential Inputs (ADS1256 only)
− Eight Single-Ended Inputs (ADS1256 only)
D Chopper-Stabilized Input Buffer
D Low-Noise PGA: 27nV Input-Referred Noise
D Self and System Calibration for All PGA
Settings
D 5V Tolerant SPI-Compatible Serial Interface
D Analog Supply: 5V
D Digital Supply: 1.8V to 3.6V
D Power Dissipation
− As Low as 38mW in Normal Mode
− 0.4mW in Standby Mode
The ADS1255 and ADS1256 are extremely low-noise,
24-bit analog-to-digital (A/D) converters. They provide
complete high-resolution measurement solutions for the
most demanding applications.
The converter is comprised of a 4th-order, delta-sigma
(∆Σ) modulator followed by a programmable digital filter. A
flexible input multiplexer handles differential or
single-ended signals and includes circuitry to verify the
integrity of the external sensor connected to the inputs.
The selectable input buffer greatly increases the input
impedance and the low-noise programmable gain
amplifier (PGA) provides gains from 1 to 64 in binary steps.
The programmable filter allows the user to optimize
between a resolution of up to 23 bits noise-free and a data
rate of up to 30k samples per second (SPS). The
converters offer fast channel cycling for measuring
multiplexed inputs and can also perform one-shot
conversions that settle in just a single cycle.
Communication is handled over an SPI-compatible serial
interface that can operate with a 2-wire connection.
Onboard calibration supports both self and system
correction of offset and gain errors for all the PGA settings.
Bidirectional digital I/Os and a programmable clock output
driver are provided for general use. The ADS1255 is
packaged in an SSOP-20, and the ADS1256 in an
SSOP-28.
APPLICATIONS
D Weigh Scales
D Scientific Instrumentation
D Industrial Process Control
D Medical Equipment
D Test and Measurement
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AINCOM
AVDD
Mux
and
Sensor
Detect
Buffer
VREFP VREFN
DVDD
1:64
PGA
Clock
Generator
XTAL1/CLKIN
XTAL2
4th−Order
Modulator
Programmable
Digital Filter
Control
General
Purpose
Digital I/O
Serial
Interface
RESET
SYNC/PDWN
DRDY
SCLK
DIN
DOUT
CS
AGND
D3 D2 D1 D0/CLKOUT
ADS1256
Only
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2003−2004, Texas Instruments Incorporated
www.ti.com






ADS1255IDBT Datasheet, Funktion
ADS1255
ADS1256
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
www.ti.com
CS
SCLK
DIN
DOUT
t3
t4
t1 t2H
t5 t6 t2L
t7 t8
Figure 1. Serial Interface Timing
t10
t11
t9
TIMING CHARACTERISTICS FOR FIGURE 1
SYMBOL DESCRIPTION
t1 SCLK period
t2H SCLK pulse width: high
t2L SCLK pulse width: low
t3 CS low to first SCLK: setup time(3)
t4 Valid DIN to SCLK falling edge: setup time
t5 Valid DIN to SCLK falling edge: hold time
t6
Delay from last SCLK edge for DIN to first SCLK rising edge for DOUT: RDATA, RDATAC,
RREG Commands
t7 SCLK rising edge to valid new DOUT: propagation delay(4)
t8 SCLK rising edge to DOUT invalid: hold time
t9
Last SCLK falling edge to DOUT high impedance
NOTE: DOUT goes high impedance immediately when CS goes high
t10 CS low after final SCLK falling edge
RREG, WREG, RDATA
t11
Final SCLK falling edge of command to first SCLK
rising edge of next command.
RDATAC, RESET, SYNC
RDATAC, STANDBY, SELFOCAL, SY-
SOCAL, SELFGCAL,
SYSGCAL, SELFCAL
(1) τCLKIN = master clock period = 1/fCLKIN.
(2) τDATA = output data period 1/fDATA.
(3) CS can be tied low.
(4) DOUT load = 20pF  100kto DGND.
MIN MAX UNIT
4 τCLKIN(1)
10 τDATA(2)
200 ns
9 τDATA
200 ns
0 ns
50 ns
50 ns
50 τCLKIN
50 ns
0 ns
6 10 τCLKIN
0 ns
4 τCLKIN
24 τCLKIN
Wait for DRDY to go low
6

6 Page









ADS1255IDBT pdf, datenblatt
ADS1255
ADS1256
SBAS288D − JUNE 2003 − REVISED AUGUST 2004
NOISE PERFORMANCE
The ADS1255/6 offer outstanding noise performance that
can be optimized by adjusting the data rate or PGA setting.
As the averaging is increased by reducing the data rate,
the noise drops correspondingly. The PGA reduces the
input-referred noise when measuring lower level signals.
Table 1 through Table 6 summarize the typical noise
performance with the inputs shorted externally. In all six
tables, the following conditions apply: T = +25°C,
AVDD = 5V, DVDD = 1.8V, VREF = 2.5V, and fCLKIN =
7.68MHz. Table 1 to Table 3 reflect the device input buffer
enabled. Table 1 shows the rms value of the input-referred
noise in volts. Table 2 shows the effective number of bits
of resolution (ENOB), using the noise data from Table 1.
ENOB is defined as:
lnǒFSRńRMS NoiseǓ
ENOB +
ln(2)
where FSR is the full-scale range. Table 3 shows the
noise-free bits of resolution. It is calculated with the same
formula as ENOB except the peak-to-peak noise value is
used instead of rms noise. Table 4 through Table 6 show
the same noise data, but with the input buffer disabled.
Table 1. Input Referred Noise (µV, rms)
with Buffer On
DATA
RATE
(SPS)
2.5
5
10
15
25
30
50
60
100
500
1000
2000
3750
7500
15,000
30,000
1
0.247
0.301
0.339
0.401
0.494
0.533
0.629
0.692
0.875
1.946
2.931
4.173
5.394
7.249
9.074
10.728
PGA
248
0.156
0.175
0.214
0.264
0.305
0.335
0.393
0.438
0.589
1.250
1.891
2.589
3.460
4.593
5.921
6.705
0.080
0.102
0.138
0.169
0.224
0.245
0.292
0.321
0.409
0.630
1.325
1.827
2.376
3.149
3.961
4.446
0.056
0.076
0.106
0.126
0.149
0.176
0.216
0.233
0.305
0.648
1.070
1.492
1.865
2.436
2.984
3.280
16
0.043
0.061
0.082
0.107
0.134
0.138
0.168
0.184
0.229
0.497
0.689
0.943
1.224
1.691
2.125
2.416
32
0.037
0.045
0.061
0.085
0.102
0.104
0.136
0.146
0.170
0.390
0.512
0.692
0.912
1.234
1.517
1.785
64
0.033
0.044
0.061
0.073
0.093
0.106
0.122
0.131
0.169
0.367
0.486
0.654
0.906
1.187
1.515
1.742
www.ti.com
Table 2. Effective Number of Bits (ENOB, rms)
with Buffer On
DATA
PGA
RATE
(SPS) 1 2 4 8 16 32 64
2.5 25.3 24.9 24.9 24.4 23.8 23.0 22.2
5 25.0 24.8 24.5 24.0 23.3 22.7 21.8
10 24.8 24.5 24.1 23.5 22.9 22.3 21.3
15 24.6 24.2 23.8 23.2 22.5 21.8 21.0
25 24.3 24.0 23.4 23.0 22.2 21.5 20.7
30 24.2 23.8 23.3 22.8 22.1 21.5 20.5
50 23.9 23.6 23.0 22.5 21.8 21.1 20.3
60 23.8 23.4 22.9 22.4 21.7 21.0 20.2
100 23.4 23.0 22.5 22.0 21.4 20.8 19.8
500 22.3 21.9 21.5 20.9 20.3 19.6 18.7
1000 21.7 21.3 20.8 20.2 19.8 19.2 18.3
2000 21.2 20.9 20.4 19.7 19.3 18.8 17.9
3750 20.8 20.5 20.0 19.4 19.0 18.4 17.4
7500 20.4 20.1 19.6 19.0 18.5 17.9 17.0
15,000 20.1 19.7 19.3 18.7 18.2 17.7 16.7
30,000 19.8 19.5 19.1 18.5 18.0 17.4 16.5
Table 3. Noise-Free Resolution (bits)
with Buffer On
DATA
PGA
RATE
(SPS) 1 2 4 8 16 32 64
2.5 23.0 22.6 22.1 21.7 21.3 20.8 19.7
5 22.3 22.4 21.9 21.3 20.7 20.3 19.3
10 22.3 22.0 21.6 21.0 20.4 19.9 18.9
15 22.0 21.7 21.3 20.7 20.1 19.3 18.7
25 21.7 21.4 21.1 20.5 19.7 19.2 18.5
30 21.8 21.3 20.8 20.4 19.8 19.0 18.1
50 21.3 21.1 20.4 19.9 19.4 18.8 17.9
60 21.3 20.9 20.5 19.8 19.3 18.8 17.8
100 20.9 20.7 20.2 19.6 19.1 18.5 17.4
500 20.1 19.6 19.1 18.6 18.0 17.3 16.3
1000 19.0 18.6 18.1 17.5 17.2 16.5 15.6
2000 18.5 18.1 17.8 17.0 16.6 16.1 15.3
3750 18.1 17.8 17.3 16.6 16.2 15.7 14.7
7500 17.7 17.3 16.9 16.2 15.8 15.3 14.4
15,000 17.3 17.0 16.5 15.9 15.5 14.9 13.9
30,000 17.1 16.7 16.4 15.9 15.4 14.6 13.8
12

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