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ADS1254E Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS1254E
Beschreibung 24-Bit/ 20kHz/ Low Power ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 17 Seiten
ADS1254E Datasheet, Funktion
ADS1254
ADS1254
SBAS213 – JUNE 2001
24-Bit, 20kHz, Low Power
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 24 BITS—NO MISSING CODES
q 19 BITS EFFECTIVE RESOLUTION UP TO
20kHz DATA RATE
q LOW NOISE: 1.8ppm
q FOUR DIFFERENTIAL INPUTS
q INL: 15ppm (max)
q EXTERNAL REFERENCE (0.5V to 5V)
q POWER-DOWN MODE
q SYNC MODE
q LOW POWER: 4mW at 20kHz
q SEPARATE DIGITAL INTERFACE SUPPLY 1.8V
to 3.6V
APPLICATIONS
q CARDIAC DIAGNOSTICS
q DIRECT THERMOCOUPLE INTERFACES
q BLOOD ANALYSIS
q INFRARED PYROMETERS
q LIQUID/GAS CHROMATOGRAPHY
q PRECISION PROCESS CONTROL
DESCRIPTION
The ADS1254 is a precision, wide dynamic range, delta-
sigma, Analog-to-Digital (A/D) converter with 24-bit reso-
lution. The delta-sigma architecture is used for wide dy-
namic range and to ensure 24 bits of no missing codes
performance. An effective resolution of 19 bits (1.8ppm of
rms noise) is achieved for conversion rates up to 20kHz.
The ADS1254 is designed for high-resolution measurement
applications in cardiac diagnostics, smart transmitters, in-
dustrial process control, weight scales, chromatography, and
portable instrumentation. The converter includes a flexible,
two-wire synchronous serial interface for low-cost isolation.
The ADS1254 is a multi-channel converter and is offered in
an SSOP-20 package.
CH1+
CH1
CH2+
CH2
CH3+
CH3
CH4+
CH4
ADS1254
Mux
4th-Order
∆Σ
Modulator
Digital
Filter
Serial
Interface
Control
VREF
CLK
SCLK
DOUT/DRDY
AVDD
AGND
DVDD
DGND
CHSEL0 CHSEL1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2001, Texas Instruments Incorporated






ADS1254E Datasheet, Funktion
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = +5V, DVDD = +1.8V, CLK = 8MHz, and VREF = 4.096, unless otherwise specified.
50
60
70
80
90
100
110
0
CMR AT 60Hz vs CLK FREQUENCY
1 234 567
Clock Frequency (MHz)
8
70
75
80
85
90
95
100
105
10
CMR vs COMMON-MODE FREQUENCY
100 1k 10k
Common-Mode Signal Frequency (Hz)
100k
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
40
CURRENT vs TEMPERATURE
AVDD (5V)
DVDD (1.8V)
20 0
20 40 60 80 100
Temperature (°C)
35
30
25
20
15
10
5
0
0
VREF CURRENT vs CLK FREQUENCY
1234567
Clock Frequency (MHz)
8
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
POWER DISSIPATION vs CLK FREQUENCY
Analog (5V)
Digital (3.3V)
Digital (1.8V)
123 4567 8
Clock Frequency (MHz)
0
20
40
60
80
100
120
140
160
0
TYPICAL FFT
(1kHz input at 0.1dB less than full-scale)
1 2 3 4 5 6 7 8 9 10 11
Input Signal Frequency (kHz)
6 ADS1254
SBAS213

6 Page









ADS1254E pdf, datenblatt
SERIAL INTERFACE
The ADS1254 includes a simple serial interface that can be
connected to microcontrollers and digital signal processors
in a variety of ways. Communications with the ADS1254
can commence on the first detection of the DOUT/DRDY
pulse after power up.
It is important to note that the data from the ADS1254 is a
24-bit result transmitted MSB-first in Offset Two’s Comple-
ment format, as shown in Table IV.
The data must be clocked out before the ADS1254 enters
DRDY mode to ensure reception of valid data, as described
in the DOUT/DRDY section of this data sheet.
ISOLATION
The serial interface of the ADS1254 provides for simple
isolation methods. The CLK signal can be local to the
ADS1254, which then only requires two signals (SCLK and
DOUT/DRDY) to be used for isolated data acquisition. The
channel select signals (CHSEL0, CHSEL1) will also need to
be isolated unless a counter is used to auto multiplex the
channels.
DIFFERENTIAL VOLTAGE INPUT
DIGITAL OUTPUT (HEX)
+Full Scale
Zero
Full Scale
7FFFFFH
000000H
800000H
TABLE IV. ADS1254 Data Format (Offset Two's Comple-
ment).
SYMBOL
tOSC
tDRDY
DRDY Mode
DOUT Mode
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
DESCRIPTION
CLK Period
Conversion Cycle
DRDY Mode
DOUT Mode
DOR Write Time
DOUT/DRDY LOW Time
DOUT/DRDY HIGH Time (Prior to Data Out)
DOUT/DRDY HIGH Time (Prior to Data Ready)
Rising Edge of CLK to Falling Edge of DOUT/DRDY
End of DRDY Mode to Rising Edge of First SCLK
End of DRDY Mode to Data Valid (Propagation Delay)
Falling Edge of SCLK to Data Valid (Hold Time)
Falling Edge of SCLK to Next Data Out Valid (Propagation Delay)
SCLK Setup Time for Synchronization or Power Down
DOUT/DRDY Pulse for Synchronization or Power Down
Rising Edge of SCLK Until Start of Synchronization
Synchronization Time
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Rising Edge of SCLK Until Start of Power Down
Falling Edge of CLK (After SCLK Goes Low) Until Start of DRDY Mode
Falling Edge of Last DOUT/DRDY to Start of Power Down
DOUT/DRDY High Time After Mux Change.
TABLE III. Digital Timing.
MIN
125
30
5
30
1537 CLK
0.5 CLK
7681 CLK
TYP
384 tOSC
36 tOSC
348 tOSC
6 tOSC
6 tOSC
6 tOSC
24 tOSC
3 tOSC
2042.5 tOSC
2318.5 tOSC
6144.5 tOSC
2043.5 tosc
MAX
50
50
50
7679 CLK
6143.5 CLK
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DOUT/DRDY
CHSEL0, CHSEL1
DATA
t18
MUX CHANGE
FIGURE 13. Multiplexer Operation.
DATA
12 ADS1254
SBAS213

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