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PDF ADS1244IDGST Data sheet ( Hoja de datos )
| Número de pieza | ADS1244IDGST | |
| Descripción | Low-Power/ 24-Bit ANALOG-TO-DIGITAL CONVERTER | |
| Fabricantes | Burr-Brown Corporation | |
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ADS1244
ADS1244
SBAS273 – DECEMBER 2002
Low-Power, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 20-BIT EFFECTIVE RESOLUTION
q CURRENT CONSUMPTION: 90µA
q ANALOG SUPPLY: 2.5V to 5.25V
q DIGITAL SUPPLY: 1.8V to 3.6V
q ±5V DIFFERENTIAL INPUT RANGE
q 0.0002% INL (TYP), 0.0008% INL (MAX)
q SIMPLE 2-WIRE SERIAL INTERFACE
q SIMULTANEOUS 50Hz AND 60Hz REJECTION
q SINGLE CONVERSIONS WITH SLEEP MODE
q SINGLE-CYCLE SETTLING
q SELF-CALIBRATION
q WELL-SUITED FOR MULTICHANNEL SYSTEMS
q EASILY CONNECTS TO THE MSP430
APPLICATIONS
q HAND-HELD INSTRUMENTATION
q PORTABLE MEDICAL EQUIPMENT
q INDUSTRIAL PROCESS CONTROL
q WEIGH SCALES
DESCRIPTION
The ADS1244 is a 24-bit, delta-sigma Analog-to-Digital (A/D)
converter. It offers excellent performance and very low power
in an MSOP-10 package and is well suited for demanding
high-resolution measurements, especially in portable and
other space- and power-constrained systems.
A 3rd-order delta-sigma modulator and digital filter form the
basis of the A/D converter. The analog modulator has a ±5V
differential input range. The digital filter rejects both 50Hz
and 60Hz signals, completely settles in one cycle, and
outputs data at 15 samples per second.
A simple, 2-wire serial interface provides all the necessary
control. Data retrieval, self-calibration, and Sleep Mode are
handled with a few simple waveforms. When only single
conversions are needed, the ADS1244 can be shut down
(Sleep Mode) while idle between measurements to dramati-
cally reduce the overall power dissipation. Multiple ADS1244s
can be connected together to create a synchronously sam-
pling multichannel measurement system. The ADS1244 is
designed to easily connect to microcontrollers, such as the
MSP430.
The ADS1244 supports 2.5V to 5.25V analog supplies and
1.8V to 3.6V digital supplies. Power is typically less than
270µW in normal operation and less than 1µW during Sleep
Mode.
VREFP VREFN AVDD
DVDD
AINP
AINN
3rd-Order
Modulator
Digital
Filter
Serial
Interface
CLK
DRDY/DOUT
SCLK
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002, Texas Instruments Incorporated
1 page  
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified.
20
18
16
14
12
10
8
6
4
2
0
1.5
INTEGRAL NONLINEARITY vs ANALOG SUPPLY
T = –40°C
VREF = AVDD
T = 25°C
T = 85°C
2 2.5 3 3.5 4 4.5 5 5.5
Analog Supply (V)
20
18
16
14
12
10
8
6
4
2
0
1.5
INTEGRAL NONLINEARITY vs ANALOG SUPPLY
T = 85°C
VREF = AVDD/2
T = 25°C
T = –40°C
2 2.5 3 3.5 4 4.5 5 5.5
Analog Supply (V)
OFFSET vs TEMPERATURE
1
0.5
0
–0.5
–1
–45 –25 –5 15 35 55 75 95
Temperature (°C)
1.00008
GAIN vs TEMPERATURE
1.00006
1.00004
1.00002
1
0.99998
0.99996
0.99994
0.99992
0.9999
–45 –25 –5 15 35 55 75 95
Temperature (°C)
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
–5
NOISE vs INPUT SIGNAL
–3 –1
1
VIN (V)
3
5
NOISE vs TEMPERATURE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
–45 –25 –5 15 35 55 75 95
Temperature (°C)
ADS1244
SBAS273
www.ti.com
5
5 Page 
DATA RETRIEVAL
The ADS1244 continuously converts the analog input signal.
To retrieve data, wait until DRDY/DOUT goes LOW, as
shown in Figure 12. After this occurs, begin shifting out the
data by applying SCLKs. Data is shifted out Most Significant
Bit (MSB) first. It is not required to shift out all the 24 bits of
data, but the data must be retrieved before the new data is
updated (see t3) or else it will be overwritten. Avoid data
retrieval during the update period. DRDY/DOUT will remain
at the state of the last bit shifted out until it is taken HIGH (see
t7), indicating that new data is being updated.
To avoid having DRDY/DOUT remain in the state of the last
bit, shift a 25th SCLK to force DRDY/DOUT HIGH, see
Figure 13. This technique is useful when a host controlling
the ADS1244 is polling DRDY/DOUT to determine when
data is ready.
DRDY/DOUT
SCLK
Data is ready.
Data
MSB
23
22
21
t5
t3
1
t4
t4
LSB
0
t6
24
t8
New data is ready.
t7
SYMBOL DESCRIPTION
MIN MAX UNITS
t3 DRDY/DOUT LOW to first SCLK rising edge.
t4 SCLK positive or negative pulse width.
t5(1) SCLK rising edge to new data bit valid:
propagation delay.
0
100
50
ns
ns
ns
t6 SCLK rising edge to old data bit valid: hold time.
t7(2) Data updating, no read back allowed.
t8(2) Conversion time (1/data rate).
0
152
66.667
152
66.667
ns
µs
ms
NOTES: (1) Load on DRDY/DOUT = 20pF || 100kΩ. (2) Values given for fCLK = 2.4576MHz. For different
CLK frequencies, scale proportional to CLK period. For example, for fCLK = 4.9152MHz, t8 → 33.333ms.
FIGURE 12. Data Retrieval Timing.
Data is ready.
Data
DRDY/DOUT
23 22 21
0
SCLK
1
24 25
25th SCLK to force DRDY/DOUT HIGH.
FIGURE 13. Data Retrieval with DRDY/DOUT Forced HIGH Afterwards.
New data is ready.
ADS1244
SBAS273
www.ti.com
11
11 Page | ||
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| PDF Descargar | [ Datasheet ADS1244IDGST.PDF ] | |
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