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ADS1244-EVM Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer ADS1244-EVM
Beschreibung Low-Power/ 24-Bit ANALOG-TO-DIGITAL CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 19 Seiten
ADS1244-EVM Datasheet, Funktion
ADS1244
ADS1244
SBAS273 – DECEMBER 2002
Low-Power, 24-Bit
ANALOG-TO-DIGITAL CONVERTER
FEATURES
q 20-BIT EFFECTIVE RESOLUTION
q CURRENT CONSUMPTION: 90µA
q ANALOG SUPPLY: 2.5V to 5.25V
q DIGITAL SUPPLY: 1.8V to 3.6V
q ±5V DIFFERENTIAL INPUT RANGE
q 0.0002% INL (TYP), 0.0008% INL (MAX)
q SIMPLE 2-WIRE SERIAL INTERFACE
q SIMULTANEOUS 50Hz AND 60Hz REJECTION
q SINGLE CONVERSIONS WITH SLEEP MODE
q SINGLE-CYCLE SETTLING
q SELF-CALIBRATION
q WELL-SUITED FOR MULTICHANNEL SYSTEMS
q EASILY CONNECTS TO THE MSP430
APPLICATIONS
q HAND-HELD INSTRUMENTATION
q PORTABLE MEDICAL EQUIPMENT
q INDUSTRIAL PROCESS CONTROL
q WEIGH SCALES
DESCRIPTION
The ADS1244 is a 24-bit, delta-sigma Analog-to-Digital (A/D)
converter. It offers excellent performance and very low power
in an MSOP-10 package and is well suited for demanding
high-resolution measurements, especially in portable and
other space- and power-constrained systems.
A 3rd-order delta-sigma modulator and digital filter form the
basis of the A/D converter. The analog modulator has a ±5V
differential input range. The digital filter rejects both 50Hz
and 60Hz signals, completely settles in one cycle, and
outputs data at 15 samples per second.
A simple, 2-wire serial interface provides all the necessary
control. Data retrieval, self-calibration, and Sleep Mode are
handled with a few simple waveforms. When only single
conversions are needed, the ADS1244 can be shut down
(Sleep Mode) while idle between measurements to dramati-
cally reduce the overall power dissipation. Multiple ADS1244s
can be connected together to create a synchronously sam-
pling multichannel measurement system. The ADS1244 is
designed to easily connect to microcontrollers, such as the
MSP430.
The ADS1244 supports 2.5V to 5.25V analog supplies and
1.8V to 3.6V digital supplies. Power is typically less than
270µW in normal operation and less than 1µW during Sleep
Mode.
VREFP VREFN AVDD
DVDD
AINP
AINN
3rd-Order
Modulator
Digital
Filter
Serial
Interface
CLK
DRDY/DOUT
SCLK
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
www.ti.com
Copyright © 2002, Texas Instruments Incorporated






ADS1244-EVM Datasheet, Funktion
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, AVDD = +5V, DVDD = +3V, fCLK = 2.4576MHz, and VREF = +2.5V, unless otherwise specified.
1200
HISTOGRAM OF OUTPUT DATA
1000
800
600
400
200
0
4 3 2 1 0 1 2 3
ppm of FSR
4
14
13
12
11
10
9
8
7
6
0
INPUT-REFERRED NOISE vs VREF
1234
VREF (V)
5
120
100
80
60
40
20
0
1
ANALOG PSRR vs FREQUENCY
10 100 1k 10k 100k
Frequency (Hz)
120
100
80
60
40
20
0
1
DIGITAL PSRR vs FREQUENCY
10 100 1k 10k 100k
Frequency (Hz)
160
140
120
100
80
60
40
20
0
1
CMRR vs FREQUENCY
10 100 1k 10k 100k
Frequency (Hz)
6 ADS1244
www.ti.com
SBAS273

6 Page









ADS1244-EVM pdf, datenblatt
SELF-CALIBRATION
The user can initiate self-calibration at any time, though in
many applications the ADS1244s drift performance is good
enough that the self-calibration performing automatically at
power-up is all that is needed. To initiate a self-calibration,
apply at least two additional SCLKs after retrieving 24 bits of
data. Figure 14 shows the timing pattern. The 25th SCLK will
send DRDY/DOUT HIGH. The falling edge of the 26th SCLK
will begin the calibration cycle. Additional SCLK pulses may
be sent after the 26th SCLK, but try to minimize activity on
SCLK during calibration for best results.
When the calibration is complete, DRDY/DOUT will go LOW
indicating that new data is ready. There is no need to alter the
analog input signal applied to the ADS1244 during calibration,
the inputs pins are disconnected within the A/D converter and
the appropriate signals applied internally automatically. The
first conversion after a calibration is fully settled and valid for
use. The time required for a calibration depends on two
independent signals: the falling edge of SCLK and an internal
clock derived from CLK. Variations in the internal calibration
values will change the time required for calibration (t9) within
the range given by the MIN/MAX specs. t12 and t13 described
in the next section are affected likewise.
DRDY/DOUT
SCLK
23 22 21
1
0
Cal begins.
24 25 26
Data ready after cal.
23
t9
SYMBOL DESCRIPTION
MIN MAX UNITS
t9(1) First data ready after calibration.
209 210 ms
NOTE: (1) Values given for fCLK = 2.4576MHz. For different CLK frequencies, scale proportional to CLK
period.
FIGURE 14. Self-Calibration Timing.
12 ADS1244
www.ti.com
SBAS273

12 Page





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